Low noise accelerometer microsystem with highly configurable capacitive interface

Abstract

This paper presents a low noise accelerometer microsystem with a highly configurable capacitive interface circuit. A programmable capacitive readout circuit is designed to minimize the offset and gain error due to the parasitic capacitance mismatch and the process variations. The interface circuit is implemented in a 0.5 lm 2P3M CMOS technology with EEPROM. The interface circuit and MEMS sensing element are integrated in a single package, and consist the accelerometer microsystem. The supply voltage and supply current of the system are 5 V and 1.17 mA, respectively. The input range and gain are 2.5 V and 0.5 V/g, respectively. The max-min gain error and max-min offset error after calibration was measured to be 1.2% FSO and 3.3% FSO, respectively. The signal to noise ratio (SNR) and noise equivalent resolution (NER) are measured to be 93.1 dB and 110.6 lg/HHz, respectively, when a 40 Hz, 5 g sinusoidal input acceleration is applied.

Differential Capacitive Readout Circuit Using Oversampling Successive Approximation Technique

“…Compared with other similar work [20][21][22][23][24], this work consumes the least power (0.5mW), which is benefited from the low power consumption single-stage amplifier rather than powerhungry high-gain amplifiers used in other work. Compared with the work [21][22][23][24], this achieves the lowest gain error 0.07%. The work [20] has a better gain error (0.037%) than this work does, but its bandwidth is 36 times lower than that of this work.…”

“…In order to solve the problems of reduced gain accuracy in the SC-CVC and the undetermined pole in the integrator, (5) and (7) suggest that the amplifier with high gain A0 is essential. Thus one general solution is to directly improve the gain of the amplifier by using structures such as two-stage amplifier ( Fig.1 (c)) [17], [24], fold/double cascode [6], [10] and gain-boosted structure [9], [20], [23]. However, these amplifiers will increase the power consumption and supply voltage significantly, which is contradictory to the requirement of the low power consumption and low supply voltage mentioned in the 1 st paragraph of this section.…”

“…This is achieved by sacrificing part of the charging current to compensate the charge loss due to the parasitic capacitance, which results in high power consumption (7mW). Both the reference [23] and the reference [24] employ digital calibration to reduce the gain error, which results in complex system due to the use of DAC and ADC. And thus the power consumption is higher than this work.…”

A High-Performance Digital Interface Circuit for a High-Q Micro-Electromechanical System Accelerometer

“…Due to underdamping, slow corresponding output in response and poor seismic performance of high vacuum mechanical structures, there will be stability problems after constituting a high-order system with the ΣΔ modulator. Therefore, when the system of micro-accelerometers can achieve sub-μg noise level, the stability of the system should be fully considered in the digital interface circuit design of micro-accelerometers [10,11,12,13]. Aiming at the stability problem of high-precision digital micro-accelerometer interface circuit, a phase compensator circuit can be designed to provide phase compensation, enhance electrical damping and improve the system response.…”