2014
DOI: 10.1109/tmtt.2014.2315170
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Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Abstract: This paper presents a stacked RF front-end (RFE) package for wideband receiver applications. While having a power consumption of 18 mW, the flipped CMOS chip consisting of a lownoise amplifier and a quadrature down-conversion mixer stacks on a glass integrated passive device (GIPD) substrate, subsequently achieving a noise figure of 2.2-2.8 dB and a conversion gain of 23-25 dB over 1-6 GHz. Moreover, the RFE package uses a GIPD balun with a high common-mode rejection ratio and a post-distortion linearizer in t… Show more

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Cited by 8 publications
(3 citation statements)
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“…Numerous papers have proposed methods for ameliorating the noise of wideband LNAs. A flipped complementary metal-oxidesemiconductor (CMOS) LNA packaged on a GIPD substrate with high-Q GIPD inductors was proposed and produced 0.4 dB decreases in the NF [11]. Inductively coupled plasma (ICP) deeptrench technology was utilised to improve the quality factor of onchip inductors; however, the extra CMOS process steps complicated the circuit implementation [12].…”
Section: Noise-reduction Lnamentioning
confidence: 99%
“…Numerous papers have proposed methods for ameliorating the noise of wideband LNAs. A flipped complementary metal-oxidesemiconductor (CMOS) LNA packaged on a GIPD substrate with high-Q GIPD inductors was proposed and produced 0.4 dB decreases in the NF [11]. Inductively coupled plasma (ICP) deeptrench technology was utilised to improve the quality factor of onchip inductors; however, the extra CMOS process steps complicated the circuit implementation [12].…”
Section: Noise-reduction Lnamentioning
confidence: 99%
“…Several papers have proposed methods for ameliorating the noise of LNAs. A flipped CMOS glass-integrated-passive-device (GIPD) package [14] and inductively coupled plasma (ICP) deep-trench technology [15] were utilized to improve the quality factor of off-chip and on-chip inductors. However, the extra processes of CMOS GIPD flip-chips and ICP created excessive costs of package and production.…”
Section: Introductionmentioning
confidence: 99%
“…However, this method leads to higher power consumption. On the other hand, passive on-chip baluns have been extensively used due to its superior common mode rejection ratio (CMRR) while consuming no power [2], [3].…”
Section: Introductionmentioning
confidence: 99%