Low noise output stage for oversampling audio DAC

Park, Yujin; Yang, Hyung Kook; Kim, Hyun-Jong; Cho, Jun Soo; Kim, Suhwan

doi:10.1109/socc.2015.7406951

Cited by 3 publications

(1 citation statement)

References 6 publications

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“…This problem does not occur when the internal DAC is implemented by a continuous-time current-adjustment internal DAC. To overcome this problem without losing the SC circuit advantages such as good ISI and device matching characteristics, we added a T/H circuit with deglitch timing between the internal DAC and the reconstruction LPF [15]. A Sallen-Key type filter realizes a 2 nd -order LPF to suppress OBN over 40 kHz.…”

Section: Architecturementioning

confidence: 99%

A Stereo Audio Delta-Sigma DAC with 40-kHz Bandwidth and 103-dB SNR

Yang¹,

Cho²,

Park³

et al. 2018

JSTS

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A wide-band and low-noise stereo deltasigma (ΔΣ) digital-to-analog converter (DAC) for audio applications is proposed. A multi-bit quantizer with data-weighted averaging is used to reduce quantization noise and a half-band finite impulse response filter is designed to increase the speed of the ΔΣ modulator. A direct-charge-transfer switchedcapacitor DAC and a track-and-hold circuit with a deglitch timing are used to improve the operating speed and the linearity of the audio DAC. The chip is fabricated with a 0.13-μm CMOS process, which uses the supply voltages of 1.2 V for the digital domain and 3.3 V for the analog domain. The experimental results show that our audio DAC achieves 40-kHz bandwidth, 103-dB A-weighted signal-to-noise ratio, and-85-dB total harmonic distortion and noise.

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Section: Architecturementioning

confidence: 99%