Low Overhead and Fast Reaction Adaptive Clocking System for Voltage Droop Tolerance

Shang, Xinchao; Shan, Weiwei; Xiang, Yi; Wan, Liang; Fan, Ao

doi:10.1049/cje.2019.02.009

Cited by 1 publication

(2 citation statements)

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“…Therefore, the path delay variability approximately presents a Gaussian distribution at a deep logic depth (larger than 8). Combined with ( 6) and ( 7), the single-level FO4 model error is ultimately expressed as (8), which is related to the influence coefficient . That is, the smaller is, the lower is.…”

Section: γ γ γmentioning

confidence: 99%

“…4, there is a gap between the paths' delay variances and the sum of cells' delay variances, which reflects the impact of input and output conditions on a path. Therefore, the single-level FO4 metric cannot fully capture the path variation and has an error (8), which indicates that a new metric with higher accuracy is needed to describe the path's variability.…”

Section: γ γ γmentioning

confidence: 99%

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An Improved Path Delay Variability Model via Multi-Level Fan-Out-of-4 Metric for Wide-Voltage-Range Digital CMOS Circuits

Cui

Shan

Dai³

et al. 2023

Chinese J. Elect.

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In advanced CMOS technology, process, voltage, and temperature (PVT) variations increase the paths' latency in digital circuits, especially when operating at a low supply voltage. The fan-out-of-4 inverter chain (FO4 chain) metric has been proven to be a good metric to estimate the path's delay variability, whereas the previous work ignored the non-independent characteristic between the adjacent cells in a path. In this study, an improved model of path delay variability is established to describe the relationship between the paths' max-delay variability and an FO4 chain, which is based on multilevel FO4 metric and circuit-level parameters knobs (i.e., cell topology and driving strength) of the first few cells. We take the slew and load into account to improve the accuracy of this framework. Examples of 28 nm and 40 nm digital circuits show that our model conforms with Monte Carlo simulations as well as fabricated chips' measurements. It is able to model the delay variability effectively to speed up the design process with limited accuracy loss. It also provides a deeper understanding and quick estimation of the path delay variability from the near-threshold to nominal voltages. Key words -Modeling, Process, voltage, and temperature (PVT) variations, Delay variability, Digital integrated circuit and FO4 inverter chain.

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Section: γ γ γmentioning

confidence: 99%

Section: γ γ γmentioning

confidence: 99%