Low Overhead Design of Power Reconfigurable FPGA with Fine-Grained Body Biasing on 65-nm SOTB CMOS Technology

Abstract

SUMMARYA Field Programmable Gate Array (FPGA) with finegrained body biasing shows satisfactory static power reduction. Contrarily, the FPGA incurs high overhead because additional body bias selectors and electrical isolation regions are needed to program the threshold voltage (V t ) of elemental circuits such as MUX, buffer and LUT in the FPGA. In this paper, low overhead design of FPGA with fine-grained body biasing is described. The FPGA is designed and fabricated on 65-nm SOTB CMOS technology. By not only adopting a customized design rule specifying that reliability is verified by TEGs but downsizing a body bias selector, the FPGA tile area becomes small by 39% compared with the conventional design, resulting in 900 FPGA tiles with 4,4000 programmable V t regions. In addition, the chip performance is evaluated by implementing 32-bit binary counter in the supply voltage range of 0.5V from 1.2V. The counter circuit operates at a frequency of 72MHz and 14MHz with the supply voltage of 1.2V and 0.5V respectively. The static power saving of 80% in elemental circuits of the FPGA at 0.5-V supply voltage and 0.5-V reverse body bias voltage is achieved in the best case. In the whole chip including configuration memory and body bias selector in addition to elemental circuits, effective static power reduction around 30% is maintained by applying 0.3-V reverse body bias voltage at each supply voltage. key words: FPGA, programmable V t , body biasing, static power

Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device

“…The power of the bias circuit (VBIAS) increases at an exponential rate independently of the biasing and the circuits. This tendency of VBIAS had already been discovered in a previous evaluation using a 32-bit counter [5].…”

“…Control voltage VHVMH and VHVML are driven by the same voltage as VBPH and VBNL. The gate-level architecture of the bias selector is shown in [5].…”