Low phase-noise VCO utilizing modified symmetric load and partial positive feedback for FDSM

High resolution Frequency-based Delta-Sigma Modulator utilizing multi-phase quantizer

“…3 shows the VCO block diagram which includes the differential delay cells and a bias circuit. The main purpose of the bias circuit [2] is to stabilize the voltage swing of the oscillation waveform, for different tuning voltages. This bias circuit ensures the correct behavior of the symmetric load of each cell.…”

“…The frequency modulator can be improved by increasing the tuning range of the VCO frequency [2], [4]. From Eq.…”

“…3, it can be seen that high resolution of the FDSM which is determined by the tuning range for a given sampling rate can be achieved by a ring VCO with large tuning range frequency. Choosing the tail current source to be a PMOS instead of an NMOS transistor as in [2], [6] will help to reduce VCO phase noise due to decreased flicker noise. In addition, the tail current transistor can be sized longer and wider in order to reduce flicker noise.…”

“…In addition, the tail current transistor can be sized longer and wider in order to reduce flicker noise. The partial feedback [2] which is generated by transistors MP4 and MP5 provides the necessary bias condition for the circuit to oscillate. The partial feedback also increases the gain of the cell.…”

“…The phase quantizer can be implemented using a counter which detects the rising edges of the VCO output, thereby quantizing the output phase by 2π. Since the full scale of the FDSM input is determined by the maximum frequency difference of the output, the resolution of the ΔΣ modulator using a counter as a phase quantizer can be represented by [2], [4]:…”