Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]

Moloney, David; O'Brien, J.; O'Rourke, Eugene; Brianti, F.

doi:10.1109/4.701282

Cited by 16 publications

(4 citation statements)

References 11 publications

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“…Further, the summation requires data memory to sequentially store the intermediate products and partial sums. Much has been done to devise strategies in order to reduce the area required for computing MAC output [2][3][4][5]. However, data memories remain a relatively unexplored aspect even though they have significant potential of giving area and power advantage.…”

Section: Introductionmentioning

confidence: 99%

A novel low area and high performance programmable FIR filter design using dynamic random access memory

Ghosh

Sharma

Aziz

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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We present a novel low area, and high performance data memory design for storing intermediate partial products in a programmable FIR filter. The advantage in area comes because the memory is implemented as DRAM in place of frequently used SRAM. A technique of storing data with Reduced Bit Precision has been demonstrated to reduce area without compromising on round-off noise. Power advantage comes because no re-write is required in this architecture after destructive read from DRAM. At high operating frequencies, simulation results in 0.2µm technology for a 48 tap FIR filter with DRAM shows an improvement in transistor count by 50% and power by 30% over SRAM.

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Section: Introductionmentioning

confidence: 99%

A novel low area and high performance programmable FIR filter design using dynamic random access memory

Ghosh

Sharma

Aziz

2005

48th Midwest Symposium on Circuits and Systems, 2005.

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“…In comparison, an attractive method is to encode the input signals to reduce the multiplication complexity. The technique of implementing the multiplier of each tap by a modified Booth multiplier has been presented in [1,12]. However, because of the accumulation loop in each tap, the hardware cost of each tap is still too high.…”

Section: Introductionmentioning

confidence: 99%

Hardware-efficient pipelined programmable FIR filter design

Chang

Jen

2001

IEE Proceedings - Computers and Digital Techniques

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With the increasing demand for video-signal processing and transmission, high-speed programmable FIR filters are required for real-time processing. This paper presents a hardwareefficient pipelined FIR architecture with programmable coefficients. FIR operations are first reformulated into multi-bit DA form at an algorithm level. Then, at the architecture level, the (p, q) compressor, instead of Booth encoding or RAM implementation, is used for high-speed operation. Due to the simple architecture, we can easily pipeline the proposed FIR filter to the adder level and save up to half of the cost of previous designs without sacrificing performance. The presented design is useful for bit-parallel input design, which can save 36.7% of the area cost compared with previous approaches.

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“…Table 3 compares the proposed filter by earlier reported work. Except for [7], each work implemented an 8-tap FIR filter with 6-bit coefficient and data. [7] reported using an average of 4.4 bits per coefficient.…”

Section: Comparison Of Various Approach-esmentioning

confidence: 99%

“…Except for [7], each work implemented an 8-tap FIR filter with 6-bit coefficient and data. [7] reported using an average of 4.4 bits per coefficient. In this table represents W/Msps/Tap/InBits/Coeff-Bits.…”

Section: Comparison Of Various Approach-esmentioning

confidence: 99%

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels

Khurshid

Staszewski

Balsara³

2000

ISLPED'00: Proceedings of the 2000 International Symposium on Low Power Electronics and Design (Cat. No.00TH8514)

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In this paper, we describe area and power reduction techniques for a low-latency adaptive finite-impulse response filter for magnetic recording read channel applications. Various techniques are used to reduce area and power dissipation while speed remains as the main performance criterion for the target application. A parallel transposed direct form architecture operates on real-time input data samples and employs a fast, low-area multiplier based on selection of radix-8 pre-multiplied coefficients in conjunction with one-hot encoded bus leading to a very compact layout and reduced power dissipation. Area, speed and power comparisons with other lowpower implementation options are also shown. The proposed filter has been fabricated using a 0.18 m L-effective CMOS technology and operates at 550 MSamples/s.

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Low-power 200-Msps, area-efficient, five-tap programmable FIR filter [in BiCMOS]

Cited by 16 publications

References 11 publications

A novel low area and high performance programmable FIR filter design using dynamic random access memory

A novel low area and high performance programmable FIR filter design using dynamic random access memory

Hardware-efficient pipelined programmable FIR filter design

Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels

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