Low-Power-Adaptive MC-CDMA Receiver Architecture

Abstract

Mohd. Hasan et al. 79This paper proposes a novel concept of adjusting the hardware size in a multi-carrier code division multiple access (MC-CDMA) receiver in real time as per the channel parameters such as delay spread, signal-to-noise ratio, transmission rate, and Doppler frequency. The fast Fourier transform (FFT) or inverse FFT (IFFT) size in orthogonal frequency division multiplexing (OFDM)/MC-CDMA transceivers varies from 1024 points to 16 points. Two low-power reconfigurable radix-4 256-point FFT processor architectures are proposed that can also be dynamically configured as 64-point and 16-point as per the channel parameters to prove the concept. By tailoring the clock of the higher FFT stages for longer FFTs and switching to shorter FFTs from longer FFTs, significant power saving is achieved. In addition, two 256 sub-carrier MC-CDMA receiver architectures are proposed which can also be configured for 64 sub-carriers in real time to prove the feasibility of the concept over the whole receiver.

Low power Multicarrier- Code Division Multiple Access Receiver on Field Programmable Gate Array

“…Figure 1 shows the block diagram of low power MC-CDMA transmitter architecture. MC-CDMA transmitter consists of a serial to parallel converter, spreading unit, inverse FFT(IFFT) unit [14], cyclic extension [2] and digital-to-analog converter (DAC) [15]. First, serial to parallel converter splits the data stream to be transmitted into N parallel streams to decrease the data rate.…”