Low-power and high-performance 5:2 compressors

Low‐power high‐performance CMOS 5‐2 compressor with 58 transistors

“…Furthermore, it has the lowest power dissipation and PDP, achieving 35.6–64.9% and 48.1–78.8% improvement, respectively. Regarding delay, it is 1.8% slower than [7] and 4.8–46.3% faster than [3–6, 8]. The post‐layout results for our circuit add an overhead of 32.8% in power and 38.5% in delay, compared to pre‐layout simulation.…”

“…According to Table 1, the proposed 5‐2 compressor has the lowest transistor count, achieving 23.6–38.3% improvement compared to [3–8]. Furthermore, it has the lowest power dissipation and PDP, achieving 35.6–64.9% and 48.1–78.8% improvement, respectively.…”

“…The post‐layout results for our circuit add an overhead of 32.8% in power and 38.5% in delay, compared to pre‐layout simulation. Nonetheless, power and PDP are still lower than schematic level implementations of [3–8] and delay is lower than [3, 5, 8].…”

“…The proposed 5‐2 compressor was implemented on transistor level along with several designs from the relevant literature [3–8], for the sake of comparison. In case that an examined work proposed several new designs, we chose the one that was deemed more efficient by its authors.…”

“…A 5‐2 compressor was initially used in [2] for the design of a high performance 16 × 16‐bit multiplier, however specific transistor‐level implementation was not provided. Several follow‐up publications proposed new designs for the 5‐2 compressor with different structures and performance trade‐offs [3–8].…”