Low-power and high-speed approximate 4:2 compressors for image multiplication applications in CNFETs

Rostami, Danial; Eshghi, Mohammad; Mehrabani, Yavar Safaei

doi:10.1080/00207217.2020.1858973

Cited by 7 publications

(5 citation statements)

References 33 publications

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“…Approximate computing is done better in error resilent applications for signal and image processing. Approximate compressors were proposed [1,2] and implemented in various multiplier designs for the image and signal processing applications. In ref [3] approximate subtractors proposed for various signal and image enhacement applications.…”

Section: Introductionmentioning

confidence: 99%

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Thiagarajan¹,

Vijeyakumar²,

Saravanakumar

2022

Preprint

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Approximate computing is a modern techniques for design of low power efficient arithmetic circuits for portable error resilient applications. In this work, we have proposed a Adaptive Parallel Mid-Point Filter (APMPF) architecture using proposed imprecise Max-Min Estimator (MME)targeting digital image processing. Parallel architecture for the MME can trade-off hardware at the expense of accuracy are proposed and used in the proposed APMPF. In APMPF, we use three level of sorting to estimate the mid-point of 3 x 3 window. Switching based trimmed filter is proposed for precise estimation of the selected window. Experimental Results interms of Area, Power and Delay with 90nm ASIC technology exposed that to the least, Proposed filters demonstrate 7% and 9% Area Delay Product (ADP) and Power Delay Product (PDP) reductions, respectively, compared to precise filter design.

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Section: Introductionmentioning

confidence: 99%

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Thiagarajan¹,

Vijeyakumar²,

Saravanakumar

2022

Preprint

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“…A significant number of these devices perform complex computational functions such as multimedia processing, data mining and pattern recognition. Furthermore, they need to have an intelligent and sometimes real-time interaction with their environment and/or the user (Han and Orshansky, 2013; Rostami et al , 2020; Xu et al , 2016). To better do their tasks, these systems need to have more computing power.…”

Section: Introductionmentioning

confidence: 99%

“…AC has drawn widespread attention as a promising paradigm for designing high-performance and energy-efficient circuits and systems at the nanoscale. Many modern applications, such as multimedia, mining and recognition, are naturally imprecision tolerant and do not necessarily require perfectly exact outcomes (Han and Orshansky, 2013; Rostami et al , 2020). Such applications can endure a lack of exactness and generate meaningful and utilizable results that are sufficient for human perceptual capability.…”

Section: Introductionmentioning

confidence: 99%

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

Mehrabani

Maleknejad

Rostami

et al. 2022

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Purpose Full adder cells are building blocks of arithmetic circuits and affect the performance of the entire digital system. The purpose of this study is to provide a low-power and high-performance full adder cell. Design/methodology/approach Approximate computing is a novel paradigm that is used to design low-power and high-performance circuits. In this paper, a novel 1-bit approximate full adder cell is presented using the combination of complementary metal-oxide-semiconductor, transmission gate and pass transistor logic styles. Findings Simulation results confirm the superiority of the proposed design in terms of power consumption and power–delay product (PDP) criteria compared to state-of-the-art circuits. Also, the proposed full adder cell is applied in an 8-bit ripple carry adder to accomplish image processing applications including image blending, motion detection and edge detection. The results confirm that the proposed cell has premier compromise and outperforms its counterparts. Originality/value The proposed cell consists of only 11 transistors and decreases the switching activity remarkably. Therefore, it is a low-power and low-PDP cell.

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“…Nowadays, compressors, especially 4-2 and 5-2 compressors due to their regular structures, receive a lot of attention from researchers and are widely used in the PPR stage in order to reduce the complexity, latency and power dissipation. Extensive research studies have been presented based on approximate and exact compressors [7][8][9]. Approximate computing is an emerging paradigm in the field of digital electronics that can tolerate some loss of accuracy to improve the power and speed performance.…”

Section: Introductionmentioning

confidence: 99%

“…Approximate computing is an emerging paradigm in the field of digital electronics that can tolerate some loss of accuracy to improve the power and speed performance. Two efficient approximate multipliers based on approximate 4-2 compressors in the PPR stage were presented in Ref [7,8] in CNTFET technology.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of energy‐efficient compressors based on low‐power XOR gates in carbon nanotube technology

Tavakkoli

Aminian

2021

IET Circuits, Devices & Syst

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Compressors are the fundamental components in multipliers to accumulate and reduce partial product stages in a parallel manner. This study presents several architectures for low-power 4-2 and 5-2 compressors, which are based on the proposed circuits of the full-swing and non-full-swing XOR gates in carbon nanotube field effect transistor (CNTFET) technology. The CNTFET technology has been chosen because of its unique electrical and mechanical features. The proposed circuits are investigated in terms of process, voltage and temperature variations, delay, power dissipation, energy, power-delay product (PDP) and transistor count. All the proposed and referenced designs are simulated using an HSPICE tool in a 32 nm CNTFET Stanford technology model. The results show that the proposed circuits have less PDP and power consumption than the previous work. The proposed compressors have the lowest PDP, achieving 5.8%-41.9% improvement.This is an open access article under the terms of the Creative Commons Attribution License, which permits use, distribution and reproduction in any medium, provided the original work is properly cited.

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Low-power and high-speed approximate 4:2 compressors for image multiplication applications in CNFETs

Cited by 7 publications

References 33 publications

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Design of Low Power Architecture for Approximate Parallel Mid-Point Filter

Low-power and low-energy CNFET-based approximate full adder cell for image processing applications

Design and analysis of energy‐efficient compressors based on low‐power XOR gates in carbon nanotube technology

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