Low‐power and wide‐band delay‐locked loop with switching delay line

Rezaeian, Adel; Ardeshir, Gholamreza; Gholami, Mohammad

doi:10.1002/cta.2539

Cited by 13 publications

(5 citation statements)

References 16 publications

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“…VCDL [2] VCDL [3] VCDL [4] VCDL [5] VCDL [6] VCDL [7] VCDL [8] Σ VCDL 6, it can be seen that the pulse width of the MD is expressed longer than one cycle. The wider UP signal is required, whereas the DN signal is not needed.…”

Section: Ref Vcdl [1]mentioning

confidence: 99%

“…The methods using a time-to-digital converter (TDC) [12] or extra replica delay cells [13] consumed high power and required a large area. Several studies have been conducted to solve the false locking problem caused by using this simple PD structure [2][3][4][5][6][7][8][9][10][11][12][13]. The technique in [6] using an external reset pulse makes it possible to escape from the false lock state, but does not actively respond to situations such as sudden changes in the reference signal.…”

Section: Introductionmentioning

confidence: 99%

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A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

Cho

2022

Electronics

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A delay locked loop (DLL) based on a Phase Detector, which Measures the Delay of the Voltage-controlled delay line (PD-MDV), which is tVCDL, with efficient and stable locking performance was proposed. In contrast to conventional phase detectors, the PD-MDV measures tVCDL more accurately; thus, it can always generate the correct up/down (UP/DN) pulses. The proposed technique prevents becoming stuck in the fastest operation, in which UP pulses continue to appear even when tVCDL < tREF, where tREF is the reference time, which is an input of the DLL. In the reverse case, the PD-MDV prohibits DN pulses from continuing to appear under the condition tVCDL > tREF, thereby freeing the DLL from harmonic locking and becoming stuck in the slowest operation. The proposed phase detection scheme was verified under various conditions, including process corners, temperature variations, and abrupt changes in tREF. The proposed 1.2 V, 20~200 MHz DLL with the PD-MDV was designed using the 65 nm process, with a power consumption of 0.4 mW at 200 MHz.

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Section: Ref Vcdl [1]mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

Cho

2022

Electronics

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“…Jitter and phase noise are crucial parameters that researchers are very concerned about, [22][23][24] and they are closely related. Phase noise is used to measure signal quality in the frequency domain, and clock jitter corresponds to it in the time domain.…”

Section: Structure Of the Proposed Multiphase Sampling Clockmentioning

confidence: 99%

A 10‐MHz to 50‐GHz low‐jitter multiphase clock generator for high‐speed oscilloscope in 0.15‐μm GaAs technology

Chen

et al. 2021

Circuit Theory & Apps

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The data acquisition system is widely used in electronic measuring instruments, for example, the oscilloscope. The development direction of the oscilloscope reflects the research status and development trend of the data acquisition system. Currently, the index of oscilloscopes is progressing toward a high sampling rate, and the performance of the analog-to-digital converter (ADC) has become the main bottleneck to improve the sampling rate of the acquisition system. The alternate sampling technology entails multichannel low sampling rate ADCs to achieve high sampling rate data acquisition through parallel sampling and realize data reconstruction through software.The sampling clock is the most important and difficult part of the system.For ADCs with the 100-GS/s sampling rate and 10-bit resolution, the jitter of the sampling clock needs to be in sub-100 fs along with multiple phases.Based on the principle of injection locking, a 150-GS/s sampling clock is proposed in this paper, which is implemented in a 0.15-μm GaAs process, and the 50-GHz locking range is achieved. The measurement results show that the sampling frequency is 150 GS/s, the root mean square (RMS) jitter is 63 fs with the integrated range from 1 kHz to 10 MHz, and the phase noise can meet the sampling requirements of the 10-bit oscilloscope, which can provide a clocking scheme for small and low-power ultrahigh-speed oscilloscope.

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“…Therefore, the design and optimization of the PD are essential for achieving high-performance DLLs in various applications. The conventional reset-path based PD is widely used because of its dead-zone free ability, as shown in Figure 2 [1][2][3]. The phase detector consists of two D flip-flops and an AND gate on the reset path.…”

Section: Introductionmentioning

confidence: 99%

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

Wu,

Huang,

Sun

et al. 2023

J. Phys.: Conf. Ser.

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This work presents a phase detector (PD) having dead-zone free and static phase offset improvement performance. The proposed phase detector inherits the low power consumption advantage of the conventional phase detector using two true-single-phase clocking (TSPC) DFFs. It also effectively reduces the static phase offset, even in the presence of inevitable charge pump current mismatch. And the dead-zone problem of conventional TSPC PD is overcome by using a falling edge delay inverter. The PD is implemented using a standard 180nm CMOS technology. The dimension of the PD’s layout is 11μm×16μm. Post-layout simulation shows that the power consumption is 53.8μW at 250MHz and 160μW at 800MHz. It achieves tiny static phase offset even if the charge pump has a 3.8% current mismatch.

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Low‐power and wide‐band delay‐locked loop with switching delay line

Cited by 13 publications

References 16 publications

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

A 1.2 V 0.4 mW 20~200 MHz DLL Based on Phase Detector Measuring the Delay of VCDL

A 10‐MHz to 50‐GHz low‐jitter multiphase clock generator for high‐speed oscilloscope in 0.15‐μm GaAs technology

Dead-Zone Free, Static Phase Offset Improvement Phase Detector for High Resolution and Low Jitter Delay-Locked Loop

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