Low power architecture for high speed packet classification

Abstract

Today's routers need to perform packet classification at wire speed in order to provide critical services such as traffic billing, priority routing and blocking unwanted Internet traffic. With everincreasing ruleset size and line speed, the task of implementing wire speed packet classification with reduced power consumption remains difficult. Software approaches are unable to classify packets at wire speed as line rates reach OC-768, while state of the art hardware approaches such as TCAM still consume large amounts of power. This paper presents a low power architecture for a high speed packet classifier which can meet OC-768 line rate. The architecture consists of an adaptive clocking unit which dynamically changes the clock speed of an energy efficient packet classifier to match fluctuations in traffic on a router line card. It achieves this with the help of a scheme developed to keep clock frequencies at the lowest speed capable of servicing the line card while reducing frequency switches. The low power architecture has been tested on OC-48, OC-192 and OC-768 packet traces created from real life network traces obtained from NLANR while classifying packets using synthetic rulesets containing up to 25,000 rules. Simulation results of our classifier implemented on a Cyclone 3 and Stratix 3 FPGA, and as an ASIC show that power savings of between 17-88% can be achieved, using our adaptive clocking unit rather than a fixed clock speed.

Ethernet Packet Processor for SOC Application

“…Many switches combine the two methods by using cutthrough until a certain error level is reached, then changing over to store and forward. Very few switches are strictly cut-through because this provides no error correction [2][3] [4]. Since processor based switch design is busy in collecting information required for switching and switching between port lead to latency.…”

Large-scale wire-speed packet classification on FPGAs

“…Two recent works [9,13] discuss several issues on implementing decision-tree-based packet classification algorithms on FPGA, with different motivations. Luo et al [13] propose a method called explicit range search to allow more cuts per node than the HyperCuts algorithm.…”

“…Since the authors do not implement their design on FPGA, the actual performance results are unclear. To achieve power efficiency, Kennedy et al [9] implement a simplified HyperCuts algorithm on an Altera Cyclone 3 FPGA. They store hundreds of rules in each leaf node and match them in parallel, resulting in low clock frequency (i.e.…”

Efficient packet classification on FPGAs also targeting at manageable memory consumption

“…Of course, a software-oriented solution cannot satisfy the required processing speeds. Hence, efficient hardware implementations using ASIC devices or FPGAs [22] have recently received substantial attention [2][3][4][5]. Some of the best packet classification algorithms targeting at the matching of d fields, where d>3, have O(log n) time complexity at the cost of O(n d ) space, or O((logn) d-1 ) search time at the cost of O(n) space, where n is the number of stored rules [16].…”