Low power array multiplier using modified full adder

Srikanth, S.; Banu, I. Thahira; Priya, G. Vishnu; Usha, G.

doi:10.1109/icetech.2016.7569408

Cited by 20 publications

(9 citation statements)

References 5 publications

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“…In this technique, the aim is to optimize type, number, interconnection, and the sequencing of computational modules while retaining the input/output behavior. This is a convenient way to reduce the switching capacitance in a circuit [29].…”

Section: Operation Reduction Techniquementioning

confidence: 99%

Power Optimization of Binary Multiplier Based on FPGA

Nasser¹,

Hashim²

2021

ETJ

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Section: Operation Reduction Techniquementioning

confidence: 99%

Power Optimization of Binary Multiplier Based on FPGA

Nasser¹,

Hashim²

2021

ETJ

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“…The Wallace tree multiplier recorded by Booth is determined to be 67% quicker than the Wallace tree multiplier, 53% faster than the Vedic multiplier, and 22% faster than the radix 8_booth multipliers. In [6] the series of array multipliers of different size, different delay and accuracy characteristics so one can select according to preference. In [7] the reduce multiplier power usage, a modified full adder with multiplexer is proposed.…”

Section: Introductionmentioning

confidence: 99%

Area Efficient Modified Array Multiplier

Shetty¹,

Kiran²

2021

JUSST

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Multipliers are widely used for various application like signal processing. Multipliers are used for multiplication two binary data .There are different kinds of multipliers with their own advantages and disadvantages. In this paper we implemented Array multiplier which has considerably more speed but also more area, it was implemented using pseudo NMOS logic in Cadence software and the number of transistors was reduced from 2N to N+1 which also lead to reduction in area.

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“…In modern era, the processor deals with complex arithmetic operations which need advanced addition, multiplication, and division units 1‐6. Many algorithms are proposed for advanced adders and multipliers, while division is getting less dealt.…”

Section: Introductionmentioning

confidence: 99%

Hardware‐efficient approximate logarithmic division with improved accuracy

Subhasri

Jammu

Harsha

et al. 2020

Circuit Theory & Apps

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Among all the arithmetic operations, division operation takes most of the clock cycles resulting in more path delay and higher power consumption. Many algorithms, including logarithmic division (LD), have been implemented to reduce the critical path delay and power consumption of division operation. However, there is a high possibility to further reduce these vital issues by using the novel approximate LD (ALD) algorithm. In the proposed ALD, a truncation adder is used for mantissa addition. Using this adder, the power delay product (PDP) and normalized mean error distance (NMED) are minimized. From the error analysis and hardware evaluation, it is observed that the proposed ALD using truncation adder (ALD‐TA) with an appropriate number of inexact bits achieve lower power consumption and higher accuracy than existing LDs with exact units. The normalized mean error distance of 8‐, 16‐, and 32‐bit ALD‐TA is compared with LDs of same bits and observed a decrease of up to 21%, 20%, and 21%, and the PDP has a reduction of up to 33%, 51%, and 72%, respectively. Application of ALD‐TA to image processing shows that high performance can be achieved by using ALDs than exact LDs.

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Low power array multiplier using modified full adder

Cited by 20 publications

References 5 publications

Power Optimization of Binary Multiplier Based on FPGA

Power Optimization of Binary Multiplier Based on FPGA

Area Efficient Modified Array Multiplier

Hardware‐efficient approximate logarithmic division with improved accuracy

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