Low power baseband processor for IoT terminals with long range wireless communications

Wu, Shunyao; Kang, Sung-moon; Chakrabarti, Chaitali; Lee, Hyunseok

doi:10.1109/globalsip.2016.7905938

Cited by 5 publications

(8 citation statements)

References 8 publications

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Section: Related Workmentioning

confidence: 99%

“…The comparison with prior art, Table II, shows that our work offers a power and area efficient alternative to the design of dedicated baseband processors. Indeed, by choosing approaches that lower frequency and therefore voltage, authors in [6] and [7] accept surface overheads which, in the end, result in increased power consumption.…”

Section: Dsp Processor Power Consumption Estimationmentioning

confidence: 99%

“…Luckily, both CMOS scaling and the current trend towards heterogeneous, multi-core IoT platforms can help to address this challenge [3]- [5]. In addition, recent research has proposed specialized architectures to address this challenge [6], [7]. But since developing a dedicated processor architecture is costly and resource-intensive, the present work instead focuses on a different approach based on existing and widely available 32-bit scalar processor architectures with singlecycle multiplication but no floating-point unit (FPU).…”

Section: Introductionmentioning

confidence: 99%

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Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Amor

Bernier

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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This work demonstrates an ultra-low power, software-defined wireless transceiver designed for IoT applications using an open-source 32-bit RISC-V core. The key driver behind this success is an optimized hardware/software partitioning of the receiver's digital signal processing operators. We benchmarked our architecture on an algorithm for the detection of FSK-modulated frames using a RISC-V compatible core and ARM Cortex-M series processors. We use only standard compilation tools and no assembly-level optimizations. Our results show that Bluetooth LE frames can be detected with an estimated peak core power consumption of 1.6 mW on a 28 nm FDSOI technology, and falling to less than 0.6 mW (on average) during symbol demodulation. This is achieved at nominal voltage. Compared to state of the art, our work offers a power efficient alternative to the design of dedicated baseband processors for ultra-low power software-defined radios with a low software complexity.

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Section: Related Workmentioning

confidence: 99%

Section: Dsp Processor Power Consumption Estimationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Amor

Bernier

2019

2019 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…Resolving this uncertainty is necessary for correctly applying the final block alignment (e.g. r 7 [k] in the middle plot of Figure 6). Of course, it is possible to rigorously lift this uncertainty by re-aligning, thanks to ST O int , the samples contained in all of the blocks employed to search for the down-chirps (assuming these have been stored in memory) and repeating step 3.…”

Section: B Algorithm Variants In the Ulp-sdr Contextmentioning

confidence: 99%

“…Another motivation for gaining a better understanding of the LoRa physical layer is the development of LoRa-compatible demodulation software for recently proposed ultra-low power software defined radios (ULP-SDR) [7][8] [9]. Indeed, compared to today's commodity IoT transceivers which are mostly implemented in hardware, software-based wireless transceivers enable the implementation of different physical layers on the same hardware.…”

mentioning

confidence: 99%

Low Complexity LoRa Frame Synchronization for Ultra-Low Power Software-Defined Radios

Bernier

Dehmas

Deparis

2020

IEEE Trans. Commun.

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Low power wide area (LPWA) wireless networks based on the LoRa physical layer have attracted huge attention in recent years, both from industry and from academic researchers. While this rising popularity is due to this technology's demonstrated effectiveness and low cost, unfortunately, due to their complexity, the timing and frequency synchronization algorithms required to detect LoRa-modulated frames, in the context of minimum sampling rate optimum receivers, have received little attention. The aim of this paper is to fill this gap and describe how robust frame detection can be performed while focusing on minimal complexity implementations of the proposed algorithms. The ultimate goal is to propose frame detection techniques applicable to recently proposed ultra-low power software-defined receivers.

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Software Defined Radio Platforms for Wireless Technologies

et al. 2022

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Wireless connectivity standards have been developed to meet the requirements of various applications. To support a wireless standard, a wireless transceiver should be equipped with a Radio Frequency (RF) transceiver. Traditional RF transceivers are designed and implemented on a radio chip or an embedded module in a System-on-a-Chip (SoC), ensuring small size, high performance, low power consumption, and cost. However, this traditional implementation design limits directly or indirectly the programmability and flexibility of the RF transceivers. An alternative solution is to implement RF transceivers using Software Defined Radio (SDR) platforms. In the market, SDR platform hardware exists with different configurations, performance, cost, size, etc., making it hard to select the minimum SDR platform necessary to satisfy the wireless standard requirements. This paper aims to provide a list of wellknown General Purpose Processor (GPP) based SDR platforms satisfying the minimum specifications of selected wireless standards. To this end, we first review the characteristics of selected wireless technologies. Then, we investigate existing SDR platform architecture and their maximal performance in terms of the frequency range, bandwidth, symbol rate, bitrate, and latency support. Finally, we intersect the wireless standard requirements with the corresponding SDR platform parameters and provide a list of GPP-based SDR platforms for some existing wireless technology implementations. While investigations related to frequency, bandwidth, symbol rate and bitrate are supported by theoretical results, latency is obtained from experiments by benchmarking existing implementations.

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Low power baseband processor for IoT terminals with long range wireless communications

Cited by 5 publications

References 8 publications

Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Software-Hardware Co-Design of Multi-Standard Digital Baseband Processor for IoT

Low Complexity LoRa Frame Synchronization for Ultra-Low Power Software-Defined Radios

Software Defined Radio Platforms for Wireless Technologies

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