Low-power bootstrapped sample and hold circuit for analog-to-digital converters

Nazzal, Tasnim B.; Mahmoud, Soliman A.

doi:10.1109/mwscas.2016.7870027

Cited by 13 publications

(11 citation statements)

References 7 publications

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“…In general, the proposed circuit shows better performance than other work. Compared with the same bootstrapping technique [12], the proposed circuit also shows better SNDR and higher sampling rate.…”

Section: Simulation Resultsmentioning

confidence: 99%

“…This technique shows decent performance to decrease charge injection and clock feedthrough effect, but the complex clocking phase in this technique rises another problem in system complexity. Several other techniques also have been reported, such as the use of current conveyor as analog switch, current controlled ISSN: 2088-8708 current mirror switching, distributed S/H, substrate-biasing-effect attenuated T switch [10], cross couple switch capacitor network, offset cancellation replica circuit [11], bootstrapping techniques [12], and other techniques [13,14,15,16]. For open-loop S/H circuit the bootstrapping technique is a suitable one, this technique keeps the gate-source voltage of sampling transistor fix at particular value.…”

Section: Channel Charge Injection Clock Feedthrough and On-resistancmentioning

confidence: 99%

“…To solve the problems presented in section 2., a new bootstrapped S/H circuit with TG switch is proposed. As depicted in Figure. 3, unlike the common bootstrap circuit [12], the proposed circuit is made up of CMOS TG switch and novel bootstrap circuit structure for each transistor in TG switch (NMOS bootstrap circuit and PMOS bootstrap circuit). The proposed circuit is operated in differential mode, but for simplicity, Figure. is on, the output of this circuit which is connected to the gate of NMOS in TG switch is connected to ground (V gn = 0).…”

Section: Proposed S/h Circuitmentioning

confidence: 99%

See 2 more Smart Citations

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

Setiabudi¹,

Tamura²,

Tanno³

2018

IJECE

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<p>A new high speed, low pedestal error bootstrapped CMOS sample and hold (S/H) circuit is proposed for high speed analog-to-digital converter (ADC). The proposed circuit is made up of CMOS transmission gate (TG) switch and two new bootstrap circuits for each transistor in TG switch. Both TG switch and bootstrap circuits are used to decrease channel charge injection and on-resistance input signal dependency. In result, distortion can be reduced. The decrease of channel charge injection input signal dependency also makes the minimizing of pedestal error by adjusting the width of NMOS and PMOS of TG switch possible. The performance of the proposed circuit was evaluated using HSPICE 0.18-m CMOS process. For 50 MHz sinusoidal 1 V peak-to-peak differential input signal with a 1 GHz sampling clock, the proposed circuit achieves 2.75 mV maximum pedestal error, 0.542 mW power consumption, 90.87 dB SNR, 73.50 SINAD which is equal to 11.92 bits ENOB, -73.58 dB THD, and 73.95 dB SFDR.</p>

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Section: Simulation Resultsmentioning

confidence: 99%

Section: Channel Charge Injection Clock Feedthrough and On-resistancmentioning

confidence: 99%

Section: Proposed S/h Circuitmentioning

confidence: 99%

See 1 more Smart Citation

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

Setiabudi¹,

Tamura²,

Tanno³

2018

IJECE

View full text Add to dashboard Cite

show abstract

“…Some techniques have been developed by many researchers to decrease hold error voltage in S/H circuit [12][13][14][15][16][17][18][19][20][21]. Most of them use an additional circuit to decrease the hold error.…”

Section: Proposed Methodsmentioning

confidence: 99%

“…The solution of this equation can be obtained by forming simultaneous equation from this basic equation. A simultaneous equation can be formed by doing two preliminary simulations with a different value of W P and W N , so that it is obtained equation (21). This equation then can be solved to get the value of L ovN and L ovP .…”

Section: Proposed Methodsmentioning

confidence: 99%

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Setiabudi

Tamura

Tanno

2018

International Journal on Advanced Science, Engineering and Information Technology

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Sample and Hold (S/H) circuit is one of the most important circuits in analog and mixed signal integrated circuit. This circuit is the main block of many applications, such as switched capacitor circuit, analog to digital converter (ADC), etc. The majority of S/H circuits are implemented using MOS technology because the high input impedance of MOS devices performs excellent holding functions. Ideal characteristics of the S/H circuit are low hold error, low On-resistance and constant On-resistance in all voltage levels. There are some techniques to reduce the hold error and achieve low On-resistance. However, these techniques need additional compensation circuit. For this reason, a simple transistors width adjustment method on CMOS transmission gate (TG) switch to reduce hold error of S/H circuit without additional circuit that can be implemented in the actual design process is proposed in this paper. The basic idea of the proposed method is balancing hold error caused by N-type and P-type MOS transistor in CMOS switch that is used in S/H circuit. The performance of the proposed method is evaluated using HSPICE with 0.6 µm CMOS standard process. As a result, using 1.5 V constant input in the PMOS transistor width W P range of 3 to 35 µm the average W N /W P ratio given by this proposed method is 0.928 with the average absolute hold error is 0.427 mV and maximum absolute hold error is 0.8 mV.

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Analysis and Design of High Performance Analog Switch Circuit Based on 0.25 μm BCD Process

Peng

Jin²

2022

Circuits Syst Signal Process

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Low-power bootstrapped sample and hold circuit for analog-to-digital converters

Cited by 13 publications

References 7 publications

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

High Speed and Low Pedestal Error Bootstrapped CMOS Sample and Hold Circuit

A Simple Transistors Width Adjustment Method on CMOS Transmission Gate Switch to Reduce Hold Error of S/H Circuit

Analysis and Design of High Performance Analog Switch Circuit Based on 0.25 μm BCD Process

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