Low-power circuit implementation for partial-product addition using pass-transistor logic

Law, Chong-Fatt; Rofail, S.S.; Yeo, Kiat Seng

doi:10.1049/ip-cds:19990328

Cited by 17 publications

(5 citation statements)

References 8 publications

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“…Conventional implementation of 4-to-2 compressor using XOR gates and MUX cells is described in Refs. [13][14][15]. This structure composed of four 2-way 2-input XOR gates and two multiplexers (MUX) and involves a critical path delay of three XOR gates delay.…”

Section: Related Workmentioning

confidence: 99%

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A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

Bagherizadeh

Eshghi

2016

j comput theor nanosci

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This paper presents a high speed design of 4-to-2 compressor, using Carbon Nanotube Field Effect Transistor (CNFET). CNFET is very suitable for low-voltage and high-frequency applications. Several conventional and state-of-the-art 4-to-2 compressor cells are also surveyed and compared in this paper. All designs are simulated by HSPICE with 32 nm CNFET technology. These designs have also been simulated at different supply voltage and different frequencies, load capacitors, and temperatures. The simulation results confirm that the proposed design is the fastest 4-to-2 compressor in different working circumstance.

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Section: Related Workmentioning

confidence: 99%

“…Different designs and architectures for 4-to-2 compressor circuits presented in literature [13][14][15][16][17][18][19][20][21][22]. A 4-to-2 compressor can be constructed using two 3-to-2 compressors (full adders) in series, shown in Figure 1.…”

Section: Related Workmentioning

confidence: 99%

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

Bagherizadeh

Eshghi

2016

j comput theor nanosci

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“…We have designed three different (8×8, 16×16 and 24×24) multipliers using Wallace tree architecture (Law et al, 1999). These multipliers uses higher order compressors.…”

Section: Multiplier Architecturementioning

confidence: 99%

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

Marimuthu¹

2013

American Journal of Applied Sciences

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This study presents higher order compressors which can be effectively used for high speed multiplications. The proposed compressors offer less delay and area. But the Energy Delay Product (EDP) is slightly higher than lower order compressors. The performance of 8×8, 16×16 and 24×24 multipliers using the proposed higher order compressors has been compared with the same multipliers using lower order compressors and found that the new structures can be used for high speed multiplications. These compressors are simulated with Cadence RTL complier at a temperature of 25°C with the supply voltage of 1.2 V.

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“…Based on this idea, a number of fancy techniques, such as Dynamic Voltage Scaling (DVS) [4] and Clustered Voltage Scaling (CVS) [5,6] have been developed. On the implementation level, numerous attempts have been undertaken to optimize almost every aspect of the processor [7][8][9]. There are also other novel techniques, such as decode filter cache [10] and computational result cache [11], which exploit the temporal locality of the programs to reduce power usage.…”

Section: Prior Workmentioning

confidence: 99%

An energy-efficient adaptive multiple-issue architecture

Lan¹,

Biglari-Abhari²

2004

Euromicro Symposium on Digital System Design, 2004. DSD 2004.

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Energy-efficient and low-power designs issues are becoming more important in modern processors. In this paper we propose an energy-efficient adaptive multiple-issue architecture for portable systems. The architecture utilizes a hardware-software cooperation approach to minimize hardware overhead while providing control flexibilities to programs and operating systems. Optimizations are made based on the program execution profile. Simulation results show that the adaptive architecture improves the performance by an average 20% with a maximum 8% reduction in energy consumption compared with the baseline model. The increase in power dissipation is restricted to less than 6%.

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Low-power circuit implementation for partial-product addition using pass-transistor logic

Cited by 17 publications

References 8 publications

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

A New High Speed Carbon Nanotube Field Effect Transistor-Based Structure for 4-to-2 Compressor Cell

Design of 8-4 and 9-4 Compressors Forhigh Speed Multiplication

An energy-efficient adaptive multiple-issue architecture

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