Low power CMOS full adder cells

Sudsakorn, Attapon; Tooprakai, Siraphop; Dejhan, Kobchai

doi:10.1109/ecticon.2012.6254174

Cited by 9 publications

(3 citation statements)

References 4 publications

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“…When designing even fast adders, it is essential to get around the rippling effect of the carry. The carry-lookahead (CLA) principle offers a possible way to ensures that a carry-bit will be generated at C out (C i ) independent of C in (C i-1 ), respectively, as shown in equation (10)(11)(12)(13).…”

Section: Carry-lookahead Addermentioning

confidence: 99%

“…Double Pass-Transistor Logic (DPL) XOR_E in Fig. (9) has 10 transistors include two inverters uses double Pass-transistor logic in which both NMOS and PMOS logic network are used [13]. The advantages of this gate avoids the nMOSFET threshold voltage drop issue of the CPL design and eliminate the power consumption, However, the drawback of this gate is a large area because of the PMOS used (4).…”

Section: Circuit Optimization Of Xor Gatementioning

confidence: 99%

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A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder

Cheng¹,

Hu²

2014

TOEEJ

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This paper presents a comparative research of low-power and high-speed 4-bit full adder circuits. The representative adders used are a ripple carry adder (RCA) and a carry-lookahead adder (CLA). We also design a proposed carrylookahead adder (PCLA) using a new method that uses NAND gate for modification which helps in reducing the powerdelay product (PDP) for high performance applications. To yield more realistic rise and fall times in the simulations, layouts have been made in a 0.13 􀀁m process for the RCA circuit, CLA circuit and PCLA circuit. The layouts designed were simulated by HSPICE based on 130 nm CMOS technology at 1.2 V supply voltages. Four sets of frequencies were operated: 10 MHz, 50 MHz, 100 MHz and 500 MHz with 50% duty cycle in different technology corner models. A comprehensive comparison and analysis were also carried out to test the performance of the adders. The three adders also yield different performances in terms of power consumption, PDP, and area. The simulation results of this research are expected to help designers to select the appropriate 4-bit adder cell that meets their specific applications.

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Section: Carry-lookahead Addermentioning

confidence: 99%

Section: Circuit Optimization Of Xor Gatementioning

confidence: 99%

A Structured Approach for Optimizing 4-Bit Carry-Lookahead Adder

Cheng¹,

Hu²

2014

TOEEJ

View full text Add to dashboard Cite

show abstract

“…Figure (2G) has 10 transistors include two inverters uses double Pass-transistor logic in which both NMOS and PMOS logic network are used [15]. The advantages of this gate avoids the nMOSFET threshold voltage drop issue of the CPL design and eliminate the static power consumption, The problems of narrow noise margin and performance degradation at low supply voltages, which occur in CPL circuits due to the threshold voltage drop, are avoided.…”

Section: Circuit Analysis Of Adder Cell Modulesmentioning

confidence: 99%