Low Power CMOS Full Adder Cells based on Alternative Logic for High-Speed Arithmetic Applications

Abstract

As the demand for computational capabilities continues to grow, the design and optimization of arithmetic circuits have more crucial in modern digital systems. The efficient operations of these arithmetic circuits heavily depend on the performance of fundamental modules such as Full Adders (FA). In addition to addressing typical challenges, designing full adder circuits using alternative logic offers unique advantages that are vital for the developing landscape of digital system. This paper presents two FAs based an alternative structures using modified Double Pass-Transistor Logic (DPL) for fast computing. The proposed Multiplexer based alternative structure differs from other conventional structures by concurrently generating both the carry signal and the sum signal, significantly reducing the overall propagation time. In addition to that multiplexers are controlled by external signals, the proposed structures provide full swing outputs. Also the modified DPL improves the signal integrity and noise immunity. The proposed circuits' performances were compared with other conventional logic and few hybrid adders. In comparison with other logics, various type of simulation results indicate that the proposed FA-2 exhibits improved performance in terms of average power, average delay, and average power-delay product (PDP). Our proposed FA-2 shows performance improvement over conventional CMOS for Power, Delay, and PDP, with values of 3.304%, 69.017%, and 74.602%, respectively. Full adders were simulated under different supply voltages and process corners to measure the reliability and robustness. Noise tolerances of full adder circuits were calculated using Average Noise Threshold Energy (ANTE) methodology.