Low-Power CMOS Synchronous Counter With Clock Gating Embedded Into Carry Propagation

Abstract

A novel low-power CMOS synchronous counter whose clock-gating logic is embedded into a carry propagation circuit is proposed. The proposed synchronous counter operates with no redundant transitions and requires fewer transistors, minimizing the switching power consumption and silicon area as compared with conventional CMOS synchronous counters. The proposed synchronous counter consisting of 16 bits was fabricated in 0.18-μm CMOS technology. The experimental result indicates that the proposed synchronous counter achieves a power saving of 64% with 15% device count reduction.

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

“…Fig. 4 Comparison of (a) proposed and (b) conventional synchronized 1/8divider (derived from [4]) chronous because of the common retiming applied to each divider output signal, and (3) there are only FFs but no other logical gates, which enables a compact and uniform layout style supporting the high-speed operation.…”

“…Examples using this approach are given in [3,4]. The synchronous frequency divider design presented in this work eliminates the drawbacks of the design methods shown in [1][2][3][4] in terms of accumulating propagation delay through the chain of divider stages or extra gates by applying a cascaded retiming method applied to each divider stage individually so that the propagation delay through the chain of divider stages does not pile up. Consequently, the maximum operation speed is determined by the retiming of a single-divider stage regardless of the value of the frequency division factor, which makes the frequency divider faster compared to conventional synchronization methods.…”

“…The second approach enforces the phase synchronization with combinatorial logic that conditions the divider outputs such that they become phase aligned. Examples using this approach are given in [3,4]. The synchronous frequency divider design presented in this work eliminates the drawbacks of the design methods shown in [1][2][3][4] in terms of accumulating propagation delay through the chain of divider stages or extra gates by applying a cascaded retiming method applied to each divider stage individually so that the propagation delay through the chain of divider stages does not pile up.…”

Power Efficient Multiplexer Using DLDFF Synchronous Counter

“…We propose a counter using our modified DLDFF in a power efficient counter architecture [6]. Here, we brief on The operation principle of the Young's synchronous counter can be understood by considering the operation of the lower four-bits.…”

“…The 8 bit synchronous counter architecture shown inFigure.4 is based on the conditional pulse synchronous timing principle[6]. The counter consists of 8 Local Clock Generator (LCGs) and 8 flip-flops.…”