Low-Power-Consumption Direct-Conversion CMOS Transceiver for Multi-Standard 5-GHz Wireless LAN Systems With Channel Bandwidths of 5–20 MHz

Abstract

This paper describes a low-power-consumption direct-conversion CMOS transceiver for WLAN systems operating at 4.9-5.95 GHz. Its power consumption is reduced by using a resonator-switching wide-dynamic-range LNA. The broad tuning range needed for multiple-channel-bandwidth systems is provided by a single widely tunable low-pass filter based on negative-source-degeneration-resistor transconductors, and its automatic frequency-band-selection PLL supports multiple standard 5-GHz WLAN systems. The system noise figure is 4.4 dB at a maximum gain of 74 dB, and the receiver IIP3 is +5 dBm and 21 dBm for the minimum and maximum gain modes, respectively. The error vector magnitude (EVM) of the transmitted signal is 2.6%. The current consumption is extremely low, 65 mA in the transmitter path and 60 mA in the receiver path.Index Terms-CMOS transceiver, frequency synthesizer, HiperLAN/2, HiSWANa, IEEE 802.11a, low-noise amplifier (LNA), low-pass filter (LPF), orthogonal frequency division multiplexing (OFDM), wireless LAN (WLAN).

A 100 MHz 2.5 GHz Direct Conversion CMOS Transceiver for SDR Applications

“…Receiver architectures must be chosen that minimize the need for filtering since low-loss, broadband tunable filters are not practical in today's technology [5]- [7]. Direct conversion is preferred for this reason, but it has some disadvantages that must be addressed through circuit techniques as discussed in Section II.…”

Design and optimization of LNA topologies with image rejection filters

“…Figure 3a shows the differential cascode LNA circuit. The circuit has several advantages because of the high IP2 of the differential amplifier that is suitable for inclusion in homodyne receivers, as well as lowering the common noise of the circuit [14]. A double-ended output can be connected directly to a double balance mixer.…”

Software‐Defined Transceivers

“…Whether on-or off-chip, cost and manufacturing issues prevent the use of huge banks of VCOs to cover SDR tuning ranges. Another way to get a broad tuning range is to have one or more VCOs and some combination of multipliers [28,29], dividers [30], or mixers [31]. Inevitably, the addition of these circuits comes at the cost of higher power consumption for equivalent noise and spurious performance.…”

“…From (2.12) we see that the frequency resolution of the system is set by the accumulator bit width, n. By using only the m MSBs of the accumulator to address the ROM, the system can maintain good frequency resolution and mitigate the power and speed penalties imposed by the ROM. Although ROM-less architectures have been developed [30,33] to reduce power consumption, the improvements have not been dramatic enough to make them viable in commercial battery-operated devices. Another promising approach to reducing DDS power consumption is the use of a digital-to-time converter (DTC) to construct an output frequency from the phase information in the accumulator.…”