Low-power content addressable memory design using two-layer P-N match-line control and sensing

Hussain, Sheikh Wasmir; Mahendra, Telajala Venkata; Mishra, Sandeep; Dandapat, Anup

doi:10.1016/j.vlsi.2020.06.001

Cited by 6 publications

(6 citation statements)

References 13 publications

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“…Since the proposed design forms a CAM word with 2 ML partitions (NAND & NOR), we focus on works with segmentation schemes [13–15, 27] and hybrid MLs [16–19, 22, 28]. In SMA‐CAM [13], a match‐line row is segmented into two sets of precharge section and charge‐shared section.…”

Section: Power‐delay Efficient Match‐line Control Unit (Mlcu) For Hyb...mentioning

confidence: 99%

“…For a legitimate comparison of the performance with the proposed design implementation, energy and delay of the referred designs are normalized using Equations ( 5) and ( 6) as presented in [4]. Reference 2016 [1] 2018 [9] 2018 [15] 2018 [20] 2019 [21] 2020 [22] 2019 [23] 2016 [25] 2017 [26]…”

Section: Performance Comparison Summarymentioning

confidence: 99%

“…P 2 SML scheme [19] is also intended for reducing the search power, but the performance degrades due to additional transistors next to every cell and sequential precharge dependence of Sigma segments to search results of multiple Pai segments. Two layers of ML, one utilising P‐type NAND cell and other using N‐type NOR cell, form a hybrid design with differential charging/discharging strategy for reducing the power consumption related to ML switching between precharges and evaluations [22]. Multi‐voltage design is another triple‐segment hybrid scheme that charges up CAM cells to different voltage domains for optimising power‐delay [28].…”

Section: Power‐delay Efficient Match‐line Control Unit (Mlcu) For Hyb...mentioning

confidence: 99%

“…Based on mismatch's pre‐decision, early termination of precharge (ETP) reduces ML swing to save power [21]. Charge‐refill technique in two‐layer ML sensing (TLMLS) design reduces the second layer's precharge and discharge levels to lessen precharge power between consecutive searches [22]. CAM design using split‐controlled single load (SCSL) cell combined with triple‐margin voltage sensing lowers leakage power and search energy [23].…”

Section: Introductionmentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

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Content addressable memory (CAM) is a hardware search engine utilised for accelerating translation and table look‐up in network routers and data processing systems. This article proposes a NAND‐NOR match‐line (ML) based CAM architecture with the main goals of elevating search performance and energy efficiency. A competent ML control unit (MLCU) is introduced to provide a short discharge path for output match‐line after processing the ML sections. In this architecture, tag mismatch based on memory traces is utilised (in NAND‐MLs) to deactivate redundant NOR‐MLs in an attempt to reduce the overall ML switching activity. Based on the decision of NAND‐ML partition, the MLCU restores the charge to reduce ML glitches during the evaluation phase. Match‐line delay of the proposed 64×32‐bit hybrid CAM is 366.90 ps in a standard 45‐nm technology at 1 V, which is 56.51% and 72.55% reductions compared to a conventional CAM and a segmented CAM, respectively. Reduction in precharge power and search power of the presented CAM leads to 6× enhancements of power‐delay‐product from existing hybrid CAMs. The proposed CAM can operate up to low supply voltages by dissipating only 0.10 fJ/bit/search at 0.5 V.

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Section: Power‐delay Efficient Match‐line Control Unit (Mlcu) For Hyb...mentioning

confidence: 99%

Section: Performance Comparison Summarymentioning

confidence: 99%

Section: Power‐delay Efficient Match‐line Control Unit (Mlcu) For Hyb...mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Match‐line control unit for power and delay reduction in hybrid CAM

Hussain

Mahendra²,

Mishra

et al. 2021

IET Circuits, Devices & Syst

Self Cite

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“…Short circuit current as well as charge sharing difficulties with conventional NAND and NOR type CAM, a novel self-controlled match line approach is presented. Therefore, the overall performance parameter was enhanced by the self-controlled circuit's ability to decrease voltage swing on mismatched matchline [15]. This summary's remaining content is arranged as follows: section 2 explains on the literature review, section 3 represents the described 45 nm SC-CAM model, simulation results is represented in section 4 and the conclusion of the paper is represented in section 5.…”

Section: Introductionmentioning

confidence: 99%

Design a self-controlled high-performance evaluation of content addressable memories using 45 nm technology

Inamanamelluri,

Dhanasekaran,

Baskar

2024

IJEECS

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A special type of random access memory (RAM) array called as content addressable memory (CAM), in which stored data is compared with the search data which can be returning the address. In the applications of highspeed searching, the CAMs are used. NOR type matchline CAMs are helpful for applications requiring faster search speeds. Because the NOR type match line (ML) CAM consumes a lot of power, therefore many published designs have attempted to reduce power consumption. The design self-controlled high-performance content addressable memories (SC-CAM) using 45-nm technology is presented in this paper. The 6T 4×4 CAM arrays in this paper uses SC logic and Tanner tools 45-nm technology. When compared to the conventional CAM, described SC-CAM architecture reduces the number of voltages sources. Described 6T 4×4 SC-CAM design needs less number of MOSFETs than existed 8T 4×4 CAM array and thus reduces the area with high speed.

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