Low-power data forwarding for VLIW embedded architectures

Abstract

Abstract-In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimization technique exploits the forwarding paths to avoid the power cost of writing/reading short-lived variables to/from the register file (RF). Such optimization is justified by the fact that, in application-specific embedded systems, a significant number of variables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived variables can thus be accessed directly through the forwarding registers, avoiding writeback to the RF by the producer instruction and successive read from the RF by the consumer instruction. The decision concerning the enabling of the RF writeback phase is taken at compile time by the compiler static scheduling algorithm. This approach implies a minimal overhead on the complexity of the processor control logic and, thus, no critical path increase. The application of the proposed solution to a VLIW embedded core has shown an average RF power saving of 7.8% with respect to the unoptimized approach on the given set of target benchmarks (patent pending owned by ST Microelectronics).Index Terms-Low-power design, microprocessors, VLSI design.

Shared-port register file architecture for low-energy VLIW processors

“…Further, if all reads of an operand can be done from the bypass network, then it need not be written to the RF at all. In VLIW processors, where the compiler is aware of the execution order, bypass usage can be determined at compile time and the relevant information passed on to the hardware either through extra bits for each operand [Sami et al 2002] or by reassignment of some architecture register addresses to point to pipeline registers instead [Goel et al 2007]. The former scheme entails a change in the instruction format, while the latter could cause a marginal performance loss.…”

“…Moreover, the fact that the average Instructions Per Cycle (IPC) for an application is less than the peak IPC also contributes to lower average usage of RF ports per cycle. Further, as shown by Goel et al [2007], Park et al [2002], and Sami et al [2002], RF read is not required for operand read from the bypass network. Bypass network, also known as forwarding paths, is a standard architectural technique implemented to avoid data hazards in processor pipelines.…”

Improving processor efficiency by statically pipelining instructions

“…al. [24] present a way to save register file power by exploiting the fact that forwarding leads to useless reads and writes. They identify these wasteful reads and writes statically in the compiler and set bits in the instructions to signify that these accesses should not be done.…”

Scalable register bypassing for FPGA-based processors

“…In related work, a number of approaches have been proposed for the evaluation of register bypassing networks [6][7][8][9][10]. Most of them deal with exploring the design space of partial bypassing for an application set, representative of a particular domain, in order to drive the customization and reduction of a full bypass network.…”

“…A design space exploration approach for eliminating infrequently used routes in register bypass networks has been presented in [8] applied to the case of a 5-issue custom VLIW processor. In a similar architectural context, low-power optimizations that exploit the forwarding paths of a fixed register bypass network, for the purpose of minimizing power-costly accesses to/from the register file have been also examined [10].…”