Low-power design by hazard filtering

Abstract

{ Before signals of a digital circuit reach steady state, gates can have multiple transitions. Since the power is dissipated in a CMOS circuit mainly due to transitions, the extra t r ansitions increase power consumption. These transitions are the hazard pulses generated by logic gates when signals arrive by paths of varying delays. The maximum width of a hazard pulse produced b y a gate is the maximum di erence b etween the delays of incident paths, which is generally much smaller than the clock period. We propose suppression of hazard pulses by increasing the delays of gates where hazards could have been generated. Thus, a hazard ltering gate has a delay which is at least as much as the di erential delay of its input paths. We give examples to illustrate the novel technique and also indicate that the overall reduction in the circuit speed may not be t o o much with proper sizing of transistors, while there c an be a signi cant reduction in power consumption.

Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing

“…To eliminate these unnecessary transitions, a designer can adopt techniques of hazard filter [7] or path balance [8]. Combined with the method of path balance, the technique of Section 3.1 can be extended to reduce leakage power and dynamic glitch power simultaneously.…”

“…Glitches can account for 20%-40% dynamic power [7]. To eliminate these unnecessary transitions, a designer can adopt techniques of hazard filter [7] or path balance [8].…”

“…However, they have not considered the glitch power, which can account for 20%-40% of the dynamic switching power [7]. To eliminate these unnec-essary transitions, a designer can adopt techniques of hazard filter [7] or path balance [8]. Raja et al [8] have proposed a technique which uses a reduced constraint set linear program (LP) to eliminate dynamic glitch power.…”

“…Nguyen et al [6] use linear programming (LP) to minimize the leakage and dynamic power by gate sizing and dual-threshold voltage devices assignment. However, they have not considered the glitch power, which can account for 20%-40% of the dynamic switching power [7]. To eliminate these unnec-essary transitions, a designer can adopt techniques of hazard filter [7] or path balance [8].…”

Input-specific Dynamic Power Optimization for VLSI Circuits

“…The principal idea in glitch reduction is to find delay assignment for all gates in the circuit to reduce the differential path delays at gate inputs with respect to the inertial delays. Optimization techniques for glitch reduction are the balanced delay [5] and hazard filtering [1] methods, implemented through a variety of algorithms such as transistor sizing [12,14], gate sizing [3,6], and linear programming [2,7,8].…”