1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96 1996
DOI: 10.1109/iscas.1996.541959
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Low-power design methodology for DSP systems using multirate approach

Abstract: We present a low-power design methodology based on the multirate approach for DSP systems. Since the data rate in the resulting multirate implementation is M-times slower (where M is a positive integer) than the original data rate while maintaining the same throughput rate, we can apply this feature to either the low-power implementation, or the speed-up of the DSP systems. This design methodology provides VLSI designers a systematic way to design low-power DSP systems at the algorithmic/architectnral level. T… Show more

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Cited by 18 publications
(16 citation statements)
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“…The dynamic power consumption of a CMOS circuit is given by (17) where is the average fraction of the total node capacitance being switched (also referred to as the activity factor), is the total switching capacitance, is the supply voltage and is the clock frequency. By employing (17), we get the ratio of the power consumption of two-stage look-ahead design, , to the power of original design, , as V V where is the original operating frequency, and represent the total switching capacitances of look-ahead and its original implementation.…”
Section: Substitutingmentioning
confidence: 99%
See 1 more Smart Citation
“…The dynamic power consumption of a CMOS circuit is given by (17) where is the average fraction of the total node capacitance being switched (also referred to as the activity factor), is the total switching capacitance, is the supply voltage and is the clock frequency. By employing (17), we get the ratio of the power consumption of two-stage look-ahead design, , to the power of original design, , as V V where is the original operating frequency, and represent the total switching capacitances of look-ahead and its original implementation.…”
Section: Substitutingmentioning
confidence: 99%
“…The multirate low-power design technique [16], [17] will be used along with other low-power design methods such as look-ahead, pipelining in our design to achieve low-power/high-speed performance. In what follows, we explain the detailed design of our compressed domain low-power video coding co-processor.…”
Section: Introductionmentioning
confidence: 99%
“…Let EXAMPLE_DSP be a digital signal pro.cessing algorithm requiring evaluation of 4-point inner products between 4-point data and coefficient vectors. Let the coefficient vector [Co, Ca, c2, c3] be equal to [13,2,9, 6] and assume that the data vector [do, d1, d2, d3] at a specific instance of the algorithm is equal to [1,3,14,2]. EXAMPLE_DSP requires computation of 4-point inner products y using the following equation:…”
Section: Motivating Examplementioning
confidence: 99%
“…In [11, 12] low power architectures for the Discrete Cosine Transform (DCT) and the Discrete Fourier Transform (DFT) are presented respectively. General methodologies for low power digital signal processing are described in [13][14][15][16].…”
Section: Introductionmentioning
confidence: 99%
“…This paper proposes a parallel context-modeling scheme based on the PPCM technique to generate several CX-D data each cycle, and a matched pipelined MQ-coder is designed to accomplish a high-performance Tier-1 coder. Since the EBCOT encoder takes most of the computation time, our proposed parallel context-modeling architecture can further be applied to the multirate approach [14] to reduce the power consumption.…”
Section: Introductionmentioning
confidence: 99%