Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

Garcia, A.; Burleson, Wayne; Danger, Jean Luc

doi:10.1109/iscas.2000.857496

Cited by 8 publications

(4 citation statements)

References 7 publications

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“…The rapid growth in the deployment of highly complex digital circuits in communication, signal processing and portable wireless applications has created a large market for low-cost, high throughput and low-power devices. Considerable research efforts over the last decade have been focused on building digital circuits that can operate at high clock frequency [1,2].…”

Section: Introductionmentioning

confidence: 99%

An Adiabatic Charge Pump Based Charge Recycling Design Style

Manne

Tyagi

2003

Lecture Notes in Computer Science

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Section: Introductionmentioning

confidence: 99%

An Adiabatic Charge Pump Based Charge Recycling Design Style

Manne

Tyagi

2003

Lecture Notes in Computer Science

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“…Noguera and Badia proposed a HW/SW co-design algorithm for dynamic reconfiguration [3]. FPGA power modeling and power-efficient design have also been studied by various researchers [6]- [10].…”

Section: Related Workmentioning

confidence: 99%

FPGA implementation of closed-loop control system for small-scale robot

Zhao

Kim

Larson

et al.

ICAR '05. Proceedings., 12th International Conference on Advanced Robotics, 2005.

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Abstract-Small robots can be beneficial to important applications such as civilian search and rescue and military surveillance, but their limited resources constrain their functionality and performance. To address this, a reconfigurable technique based on field-programmable gate arrays (FPGAs) may be applied, which has the potential for greater functionality and higher performance, but with smaller volume and lower power dissipation. This project investigates an FPGA-based PID motion control system for small, self-adaptive systems. For one channel control, parallel and serial architectures for the PID control algorithm are designed and implemented. Based on these onechannel designs, four architectures for multiple-channel control are proposed and two channel-level serial (CLS) architectures are designed and implemented. Functional correctness of all the designs was verified in motor control experiments, and area, speed, and power consumption were analyzed. The tradeoffs between the different designs are discussed in terms of area, power consumption, and execution time with respect to number of channels, sampling rate, and control clock frequency. The data gathered in this paper will be leveraged in future work to dynamically adapt the robot at run time.

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“…Then, using this model, some methods to reduce power consumption on FPGAs can be explored [5,7,8]. Finally, a tool that estimate the power consumption in FPGAs could be described.…”

Section: Power Consumption In Sram-based Fpgasmentioning

confidence: 99%

“…This can be possible by using a manual partitioning process to optimize critical pads and blocks. If the embedded cells are not used to build memory blocks, they must be used to build glue logic as needed [5,7].…”

Section: Power Optimizationmentioning

confidence: 99%

Power Consumption Management on FPGAs

Garcia

Perez

Acuna

15th International Conference on Electronics, Communications and Computers (CONIELECOMP'05)

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During the last years, the number of hardware implementations based on Field Programmable Gate Arrays (FPGAs) is increasing because it satisfies the high speed of system and hardware cost constraints. FPGAs implementation allows the building of rapid prototypes reducing development times and board area. However, since FPGAs has been improved to satisfy speed and size constraints, it is not evident that these devices could satisfy low-power consumption constraint. Compared to ASICs, FPGAs are generally perceived as non low-power consumption devices, whose only advantage is programmability and more recently dynamic reconfigurability. In this work we present an study of dynamic and static power consumption of FPGAs that allows the designer to acquire a better understanding of how power consumption is generated and distributed inside the FPGAs. Based on these results, a genetic algorithm will be used to minimize critical long paths and optimize the internal resources during the Place & Route process in order to optimize power consumption while keeping a high performance. Categories: Circuit Design

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Low power digital design in FPGAs: a study of pipeline architectures implemented in a FPGA using a low supply voltage to reduce power consumption

Cited by 8 publications

References 7 publications

An Adiabatic Charge Pump Based Charge Recycling Design Style

An Adiabatic Charge Pump Based Charge Recycling Design Style

FPGA implementation of closed-loop control system for small-scale robot

Power Consumption Management on FPGAs

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