Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformers

Jang, Sheng‐Lyang; Chang, Chih-Wei; Cheng, Wei-Yang; Lee, C.F.; Juang, Miin‐Horng

doi:10.1049/el:20092027

Cited by 11 publications

(8 citation statements)

References 4 publications

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“…Table 1 is a summary of the implemented ILFD3, and recently reported state‐of‐the‐art divide‐by‐3 CMOS dividers in Refs. 2, 4–6. As can be seen, our ILFD3 showed the widest LR, and achieved the highest FOM.…”

Section: Measurement Results and Discussionmentioning

confidence: 73%

“…The high speed MMW phase‐locked loop (PLL) is a crucial building block for developing a high speed transceiver, whereas frequency divider is a crucial building block in MMW PLL. Figure 1 shows a typical block diagram of an MMW PLL used for MMW transceiver applications, which requires a high‐speed divide‐by‐3 frequency‐divider operated in the frequency band of interest [1–6]. The percentage locking range (LR) of a divider can be defined as follows [7]: in which f max and f min are the maximum and minimum locking frequency of the divider, respectively.…”

Section: Introductionmentioning

confidence: 99%

“…Instead of the two transistors for differential signal injection, two transformers are adopted in Ref. 2. As no stacked MOSFET is used, the circuit is potential for low voltage operation (0.8 V in 0.13 μm CMOS technology).…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Wide locking range divide‐by‐3 injection‐locked frequency divider using differential‐injection linear mixers and dual frequency tuning

Wang

Chen

Lin

2011

Micro & Optical Tech Letters

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be seen, this proposed hybrid coupler has the best ability of size reduction except that in Ref. 23. However, this proposed hybrid coupler has a wider stop-band up to fourth harmonic than that in Ref. 23 and hence a better harmonics suppression.ABSTRACT: A boundary condition capable of efficiently exciting and absorbing hybrid waveguide modes is derived for use in the context of the finite element method. Its performance is assessed in two cases, that is, a silicon and a plasmonic waveguide, and compared with that of the standard absorbing boundary condition.

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Section: Measurement Results and Discussionmentioning

confidence: 73%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Wide locking range divide‐by‐3 injection‐locked frequency divider using differential‐injection linear mixers and dual frequency tuning

Wang

Chen

Lin

2011

Micro & Optical Tech Letters

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“…A popular LC-tank ILFD design uses a direct cross-coupled oscillator as the core. The divide-by-3 ILFD belongs to higher modulus ILFDs and the conventional divide-by-3 ILFD [1][2][3][4] has a limited locking range as a result of using the low conversion efficiency harmonic mixer approach. The divide-by-3 ILFD has received wide attention because it uses different device physics distinct from divide-by-2 ILFDs.…”

mentioning

confidence: 99%

Wide‐locking range class‐C injection‐locked frequency divider

Jang

Lin

2014

Electron. lett.

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A novel wide-locking range divide-by-3 injection-locked frequency divider (ILFD) is designed and fabricated in a standard 0.18 μm CMOS process. The CMOS ILFD uses a class-C capacitive crosscoupled oscillator as the core. It has been found that the locking range of the ILFD is enhanced when the DC-gate bias is smaller than the drain bias in the cross-coupled pair. At the supply voltage of 1.8 V, the core power consumption of the ILFD core is 10.7 mW. At the incident power of 0 dBm, the maximum locking range is 3.3 GHz (24.17%), from the incident frequency 12-15.3 GHz. At the incident power of 0 dBm, the operation range is 4.8 GHz (37.2%), from the incident frequency 10.5-15.3 GHz.Introduction: Fully integrated CMOS LC-tank injection-locked frequency dividers (ILFDs) play an important role in various frequency synthesisers and wireless transceivers. A popular LC-tank ILFD design uses a direct cross-coupled oscillator as the core. The divide-by-3 ILFD belongs to higher modulus ILFDs and the conventional divide-by-3 ILFD [1-4] has a limited locking range as a result of using the low conversion efficiency harmonic mixer approach. The divide-by-3 ILFD has received wide attention because it uses different device physics distinct from divide-by-2 ILFDs. The study of divide-by-3 ILFDs in the past has focused on the enhancement of locking range [5-9] using a linear mixer rather than the harmonic mixer. Owing to the past efforts, the locking range has been significantly extended. The popular divide-by-3 ILFD uses a direct cross-coupled transistor pair to sustain the same oscillation as divide-by-2 ILFDs. Using a class-B oscillator in the ILFD is extremely popular in real-life applications owing to its simplicity and robustness. With this approach, the DC-gate voltage is equal to the DC drain voltage in the cross-coupled transistors.In this Letter, we propose a divide-by-3 ILFD based on the class-C oscillator. The simple method of designing the class-C ILFD is to lower the bias voltage at the gates of cross-coupled transistors to that which is much smaller than the threshold voltage. With one more gate bias, the design window has been extended. It is well-known that the class-C oscillator has better power conversion efficiency [10][11][12][13]. Experimental results in this Letter show that the locking range of the ILFD can be significantly improved with the class-C oscillator.

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“…However, the divide-by-3 frequency divider can simplify PLL design with more flexibility. The divide-by-3 frequency divider has been well studied [1,2]. Based on the Miller divider, the circuit diagram of SDFD is composed of a mixer, N stages of CML static frequency divider and a feedback path to the mixer [3].…”

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confidence: 99%

Quadrature current-reused divide-by-3 semi-dynamic frequency divider with active balun

et al. 2012

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A divide-by-3 semi-dynamic frequency divider (SDFD) with active balun is presented using the current-reused technique. The proposed SDFD is composed of a Gilbert cell mixer, one stage of static divider and an active balun. The LO switching stage of the Gilbert cell mixer is also the current source of the static frequency divider to construct the current-reused architecture. At the incident power of 0 dBm, this frequency divider operates at the maximum bandwidth of 1100 MHz from 21.5 to 22.6 GHz. The power consumption of the divider is 12 mW at a 1.5 V supply voltage.

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Low-power divide-by-3 injection-locked frequency dividers implemented with injection transformers

Cited by 11 publications

References 4 publications

Wide locking range divide‐by‐3 injection‐locked frequency divider using differential‐injection linear mixers and dual frequency tuning

Wide locking range divide‐by‐3 injection‐locked frequency divider using differential‐injection linear mixers and dual frequency tuning

Wide‐locking range class‐C injection‐locked frequency divider

Quadrature current-reused divide-by-3 semi-dynamic frequency divider with active balun

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