Low-Power DRAM

Kotabe, Akira

doi:10.1007/978-1-4614-0812-3_5

Cited by 1 publication

(1 citation statement)

References 26 publications

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“…These structures (mats) are composed of 512 × 1024 cells ( 1 ), and each cell is connected to a column bitline ( 2 ), via an access transistor ( 3 ) [42], [46], [47]. Along a mat's row, all access transistors share the same control line, the sub-word line (SWL) ( 4 ), which is raised upon row activation by the sub-word line driver (SWD, 5 ) [48], [49]. Functionally, the SWL corresponds to the logical row selector.…”

Section: A Physical Organizationmentioning

confidence: 99%

REGA: Scalable Rowhammer Mitigation with Refresh-Generating Activations

Marazzi¹,

Solt²,

Jattke³

et al. 2023

2023 IEEE Symposium on Security and Privacy (SP)

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Mitigating Rowhammer requires performing additional refresh operations to recharge DRAM rows before bits start to flip. These refreshes are scarce and can only happen periodically, impeding the design of effective mitigations as newer DRAM substrates become more vulnerable to Rowhammer, and more "victim" rows are affected by a single "aggressor" row.We introduce REGA, the first in-DRAM mechanism that can generate extra refresh operations each time a row is activated. Since row activations are the sole cause of Rowhammer, these extra refreshes become available as soon as the DRAM device faces Rowhammer-inducing activations. Refresh operations are traditionally performed using sense amplifiers. Sense amplifiers, however, are also in charge of handling the read and write operations. Consequently, the sense amplifiers cannot be used for refreshing rows during data transfers. To enable refresh operations in parallel to data transfers, REGA uses additional low-overhead buffering sense amplifiers for the sole purpose of data transfers. REGA can then use the original sense amplifiers for parallel refresh operations of other rows during row activations.The refreshes generated by REGA enable the design of simple and scalable in-DRAM mitigations with strong security guarantees.As an example, we build REGAM, the first deterministic in-DRAM mitigation that scales to small Rowhammer thresholds while remaining agnostic to the number of victims per aggressor. REGAM has a constant 2.1% area overhead, and can protect DDR5 devices with Rowhammer thresholds as small as 261, 517, and 1029 with 23.9%, 11.5%, and 4.7% more power, and 3.7%, 0.8% and 0% performance overhead.

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