Low power dynamic comparator for 4 — bit Flash ADC

Patil, Hazrat; Raghavendra, M. J.

doi:10.1109/iccic.2016.7919550

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Flash Adc Architecture1

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Cited by 13 publications

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“…One of the challenges in a high‐speed flash ADC design is the conversion of the thermometer code to binary code [20]. The encoder is implemented using Wallace tree architecture which comprises of full adders.…”

Section: Flash Adc Architecturementioning

confidence: 99%

Highly‐digital voltage scalable 4‐bit flash ADC

Gupta

Singh

Agarwal

2018

IET Circuits, Devices & Systems

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This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

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Section: Flash Adc Architecturementioning

confidence: 99%