Low-Power Dynamic Comparator With High Precision for Sar Adc

Alaybeyoglu, Ersin

doi:10.31127/tuje.625475

Cited by 2 publications

(2 citation statements)

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“…To reduce the power consumption, there are many diferent methods, as will be demonstrated in this paper. Various confgurations for the comparator [14][15][16][17][18][19][20][21][22][23][24] can be used to reduce power consumption, time delay, and noise efects. In addition, the modifed binary-weighted CDAC structure can save area and energy.…”

Section: Sar Adc Architecturementioning

confidence: 99%

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Successive Approximation Register Analog-to-Digital Converter (SAR ADC) for Biomedical Applications

Arafa

Ellaithy

Zekry

et al. 2023

Active and Passive Electronic Components

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This study presents a survey of the most promising reported SAR ADC designs for biomedical applications, stressing advantages, disadvantages, and limitations, and concludes with a quantitative comparison. Recent progress in the development of a single SAR ADC architecture is reviewed. In wearable and biosensor systems, a very small amount of total power must be devoured by portable batteries or energy-harvesting circuits in order to function correctly. During the past decade, implementation of the high energy efficiency of SAR ADC has become the most necessary. So, several different implementation schemes for the main components of the SAR ADC have been proposed. In this review study, the various circuit architectures have been explained, beginning with the sample and hold (S/H) switching circuits, the dynamic comparator, the internal digital-to-analog converter (DAC), and the SAR control logic. In order to achieve low power consumption, numerous different configurations of dynamic comparator circuits are revealed. At the end of this overview, the evolutions of DAC architecture in distinct biomedical applications today can make a tradeoff between resolution, speed, and linearity, which represent the challenges of a single SAR ADC. For high resolution, the dual split capacitive DAC (CDAC) array technique and hybrid capacitor technique can be used. Also, for ultralow power consumption, various voltage switching schemes are achieved to reduce the number of switches. These schemes can save switching energy and reduce capacitor array area with high linearity. Additionally, to increase the speed of the conversion process, a prediction-based ADC design is employed. Therefore, SAR ADC is considered the ideal solution for biomedical applications.

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Section: Sar Adc Architecturementioning

confidence: 99%

“…In this comparator scheme, multistages of the preamplifer stage and single-stage dynamic latch are employed taking the advantages of both. In addition, rejection of the common mode voltage and external noise is achieved [21].…”

Section: Multistage Preamplifer Dynamic Latch Comparatormentioning

confidence: 99%