Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design

Abstract

This paper presents a fast low-energy full adder circuit implementation for deep-submicron technology. With rapid technology scaling, the main focus in low power design is targeted to reduce the static power while trading other vital requirements such as driving capability, delay, total power and noise immunity. Based on the fact that transmission logic has good driving capability and full signal swing than pass transistor logic, a new full adder cell is proposed to reduce delay and power-delay product (PDP). Simulations have been carried out for different supply voltages and loading conditions to compare the performance of the proposed circuit with respect to the existing ones.