Low-Power FPGA Design Using Memoization-Based Approximate Computing

Sinha, Sharad; Zhang, Wei

doi:10.1109/tvlsi.2016.2520979

Cited by 29 publications

(16 citation statements)

References 16 publications

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“…The CAM-based design is expensive and requires significant modification to the baseline GPU architecture. Sinha et al [27] proposed a memoization-based approximate computing design on FPGA. However, this proposal only works for reconfigurable logic, because it cannot handle different number of inputs without using reconfigurable logic.…”

Section: Related Workmentioning

confidence: 99%

AxMemo

Liu

Yazdanbakhsh

Wang

et al. 2019

Proceedings of the 46th International Symposium on Computer Architecture

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Historically, continuous improvements in general-purpose processors have fueled the economic success and growth of the IT industry. However, the diminishing benefits from transistor scaling and conventional optimization techniques necessitates moving beyond common practices. Approximate computing is one such unconventional technique that has shown promise in pushing the boundaries of generalpurpose processing. This paper sets out to employ approximation for processors that are commonly used in cyberphysical domains and may become building blocks of Internet of Things. To this end, we propose AxMemo to exploit the computation redundancy that stems from data similarity in the inputs of code blocks. Such input behavior is prevalent in cyber-physical systems as they deal with real-world data that naturally harbors redundancy. Therefore, in contrast to existing memoization techniques that replace costly floating-point arithmetic operations with limited number of inputs, AxMemo focuses on memoizing blocks of code with potentially many inputs. As such, AxMemo aims to replace long sequences of instructions with a few hash and lookup operations. By reducing the number of dynamic instructions, AxMemo alleviates the von Neumann and execution overheads of passing instructions through the processor pipeline altogether. The challenge AxMemo facing is to provide low-cost hashing mechanisms that can generate rather unique signature for each multi-input combination. To address this challenge, we develop a novel use of Cyclic Redundancy Checking (CRC) to hash the inputs. To increase lookup table hit rate, AxMemo employs a two-level memoization lookup, which utilizes small dedicated SRAM and spare storage in the last level cache. These solutions enable AxMemo to efficiently memoize relatively large code regions with variable input sizes and types using the same underlying hardware. Our experiment shows that AxMemo offers 2.64× speedup and 2.58× energy reduction with mere 0.2% of quality loss averaged across ten benchmarks. These benefits come with an area overhead of just 2.1%.

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Section: Related Workmentioning

confidence: 99%

AxMemo

Liu

Yazdanbakhsh

Wang

et al. 2019

Proceedings of the 46th International Symposium on Computer Architecture

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“…The same idea, known as memoization, can be applied to machine data processing 11 and can help save energy. 13 Modern computer languages, such as Python, already provide mechanisms to automatically memoize functions. 14 The reuse of computation is a memoization technique that is often used to speedup the execution of programs: it keeps track of every operation that has been executed with the same input operands and that produces the same output.…”

Section: Related Workmentioning

confidence: 99%

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

Rouberte

Sena

Nery

et al. 2018

Concurrency and Computation

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Summary Instruction Reuse is a technique adopted in Von Neumann architectures that improves performance by avoiding redundant execution of instructions when the result to be produced can be obtained by searching an input/output memoization table for such instruction. Trace reuse can be applied to traces of instructions in a similar fashion. However, those techniques are yet to be studied in the context of the Dataflow model, which has been gaining traction in the high performance computing community due to its inherent parallelism. Dataflow programs are represented by directed graphs where nodes are instructions or tasks and edges denote data dependencies between tasks. This work presents Dataflow Dynamic Task Memoization (DF‐DTM), a technique that allows the reuse of both nodes and subgraphs in dataflow, which are analogous to instructions and traces, respectively. The potential of DF‐DTM is evaluated by a series of experiments that analyze the behavior of redundant tasks in five relevant benchmarks, where up to 99.70% of the instantiated tasks could be reused. Moreover, this paper evaluates how reuse rates can be affected by limiting subgraph size, memoization table size, task granularity, and problem size, showing that DF‐DTM can yield good reuse rates in more realistic environments.

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“…Modern computer languages, such as Python, already provide mechanisms to automatically memoize functions . Implementations of memoization schemes have also been proposed for Field‐Programmable Gate Arrays (FPGAs) aimed at lowering power consumption …”

Section: Related Workmentioning

confidence: 99%

“…8 Implementations of memoization schemes have also been proposed for Field-Programmable Gate Arrays (FPGAs) aimed at lowering power consumption. 9 The memoization of redundant functions inspired several studies on the topic in the past 20 years, revisiting the concept of reuse at the micro-architectural level, where reuse tables (eg, caches) are often used to store the results of redundant instructions. An instruction or group of instructions is redundant whenever it produces the same output given the same input operands.…”

Section: Related Workmentioning

confidence: 99%

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

Marzulo

Sena

Nery

et al. 2018

Concurrency and Computation

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Summary In a program, there is usually a significant amount of instructions that are repeatedly executed with the same inputs during the execution. This redundancy allows the reuse of previous computations, potentially reducing the program execution time. The Dynamic Trace Memoization technique (DTM) was proposed to exploit the reuse of a dynamic sequence of redundant instructions for superscalar CPUs. This paper proposes the application of the DTM technique on a GPU architecture. We propose the DTM@GPU model that adapts the original DTM technique to the NVIDIA GPU architecture by introducing architectural modifications and the identification of different trace reuse styles in multithreaded environments. We investigate reuse opportunities in real‐world GPU applications and the potential performance gains. We also perform a detailed investigation on the characteristics of the reused traces. This characterization shows the number and size of the reused traces, the influence of the cache size on reuse rates, and the cycles that are saved when all threads in a warp reuse instructions or traces. The results show approximately up to 35.3% of reuse, yielding an estimated speedup gain of 10.7%.

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Low-Power FPGA Design Using Memoization-Based Approximate Computing

Cited by 29 publications

References 16 publications

AxMemo

AxMemo

DF‐DTM: Dynamic Task Memoization and reuse in dataflow

DTM@GPU: Characterizing and evaluating trace redundancy in GPU

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