2008
DOI: 10.1007/s11265-008-0253-z
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Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications

Abstract: This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan (Y/X) with a latency of two clock cycles and its power consumption is 49% lower than… Show more

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Cited by 11 publications
(14 citation statements)
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“…This can be easily performed by the architecture depicted on Figure 4 [2]. This architecture first CORDIC computation of the arctangent is classically [3],…”
Section: B Scaling Range Reductionmentioning
confidence: 99%
“…This can be easily performed by the architecture depicted on Figure 4 [2]. This architecture first CORDIC computation of the arctangent is classically [3],…”
Section: B Scaling Range Reductionmentioning
confidence: 99%
“…The proposed RPC is compared with other implementations [15] on the same target device. Whereas [15] is providing only phase, ours is computing the phase as well as the magnitude.…”
Section: Figure 6 Area Utilizationmentioning
confidence: 99%
“…Whereas [15] is providing only phase, ours is computing the phase as well as the magnitude. The comparison chart is shown in Table 1.…”
Section: Figure 6 Area Utilizationmentioning
confidence: 99%
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“…Each of these approaches requires a relevant argument reduction, which is also discussed. All the algorithms are lastbit accurate, and implemented with similar care in the opensource FloPoCo framework [2]. R. Gutierrez a, V. Torres b and J. Valls presents a paper that proposed an architecture for the computation of the atan2.…”
Section: Introductionmentioning
confidence: 99%