Low-power fully integrated 10-gb/s sonet/sdh transceiver in 0.13-μ cmos

Henrickson, L.; Shen, D.H.; Nellore, U.; Ellis, A.D.; Oh, Joong; Wang, Hui; Capriglione, G.; Atesoglu, A.; Yang, A.T.; Wu, Pan; Quadri, Quadir H.; Crosbie, D.

doi:10.1109/jssc.2003.817586

Cited by 46 publications

(23 citation statements)

References 10 publications

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“…It should be noted that OSR hf is the normalized floored half of the OSR as described in Eq. (4). For the proposed design OSR ¼5 and OSR hf ¼2/5.…”

Section: Jitter Tolerancementioning

confidence: 99%

“…Additional high performance clock multiplication unit (CMU) is typically used as a supplement to the CDR to achieve all three jitter metrics. If the CMU cannot achieve the required jitter clean-up for the CDR and the required bandwidth control an extra clean up PLL is needed [4][5][6]. A simplified block diagram of the required timing macros for both cases is shown in Fig.…”

Section: Introductionmentioning

confidence: 99%

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An all-digital semi-blind clock and data recovery system

Abdallah

Eladawy

Mohieldin

2015

Microelectronics Journal

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“…It should be noted that OSR hf is the normalized floored half of the OSR as described in Eq. (4). For the proposed design OSR ¼5 and OSR hf ¼2/5.…”

Section: Jitter Tolerancementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

An all-digital semi-blind clock and data recovery system

Abdallah

Eladawy

Mohieldin

2015

Microelectronics Journal

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“…17 [19][20][21]. The operating principle of this CDR is explained as follows: first, lock detector activates the multiplexer to turn on the frequency loop (Loop 1) and turn off the phase loop (loop 2).…”

Section: Frequency Aided Acquisition In Cdr Circuitmentioning

confidence: 99%

Design of high-speed clock and data recovery circuits

Kok-Siang

Sulaiman

Hean-Teik

et al. 2007

Analog Integr Circ Sig Process

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This article describes the various architectures for a high-speed clock and data recovery (CDR) circuit. Following a brief introduction of clock and data recovery circuit, a phase detection circuit, one of the most critical blocks in a CDR that determines not only the performance but also the CDR architecture, is addressed. The descriptions start with the most basic XOR logic up to the phasefrequency detector circuit. Trade-offs of each of the phase detectors are outlined. Two types of dual loop CDR architecture are briefly introduced. Finally, full-rate and half rate CDR architectures are described.

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“…The functional block most affected by the use of low cost plastic packages is usually the limiting amplifier, that is often the input stage of an IC [1]. Limiting amplifiers are usually designed as a cascade of two or more dc-coupled differential stages [2,3], and also include a high-gain offset suppression network that is required in order to avoid saturation of the output stage.…”

Section: Introductionmentioning

confidence: 99%

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

Centurelli¹,

Pallotta

Tommasino

et al. 2006

Analog Integr Circ Sig Process

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The diffusion of optical communication systems in the access network and for short-haul datacom applications requires the use of low-cost plastic packages: the functional block most affected is the limiting amplifier, that is often the first stage of the Clock and Data Recovery (CDR) IC.In this paper we illustrate the design issues of the input-matching and offset-cancelling network for a differential limiting amplifier for optical communication systems, with particular emphasis on the effect of bond wires. We discuss the limitations of passive feedback networks when used both for offset suppression and for input matching, and propose a topology that overcomes such limitations by using an active feedback loop. A 50 -loaded differential pair is used to achieve input matching and high offset suppression, and its buffering action desensitizes the input matching from the effect of the bond wires connecting off-chip filtering capacitors. Very good performance even with low cost plastic packages can be achieved by solving the trade-off between power consumption, offset suppression and the value of the low-pass filtering capacitors.Design examples of CDR IC's for 2.5 Gb/s optical systems are presented to compare the proposed topology with solutions based on passive feedback networks.

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Low-power fully integrated 10-gb/s sonet/sdh transceiver in 0.13-μ cmos

Cited by 46 publications

References 10 publications

An all-digital semi-blind clock and data recovery system

An all-digital semi-blind clock and data recovery system

Design of high-speed clock and data recovery circuits

Input-Matching and Offset-Cancelling Networks for Limiting Amplifiers in Optical Communication Systems

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