Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Hoang, Trong-Thuc; Duran, Ckristian; Nguyen, Khai-Duy; Dang, Tuan-Kiet; Nhu, Quynh Nguyen Quang; Than, Phuc Hong; Tran, Xuan‐Tu; Le, Duc-Hung; Tsukamoto, Akira; Suzaki, Kuniyasu; Pham, Cong‐Kha

doi:10.1587/elex.17.20200282

Cited by 8 publications

(6 citation statements)

References 18 publications

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“…The back-gate bias of the targeted microcontroller can be controlled to favor low-power or high-performance operations [31]. The supply voltage for the internal logic core can range from 0.5 V to 1.2 V, while the supply voltage for the I/O banks is fixed at 3.3 V. The microcontroller can be tuned with back-gate bias ranging from -2.0 V to 2.0 V. The maximum clock frequency that the microcontroller can operate with is F max = 156 MHz when the core supply voltage V DD = 1.2 V and back-gate bias V BB = 1.6 V. In general, this F max value linearly increases with increasing V DD and increasing back-gate bias…”

Section: B Test Devicementioning

confidence: 99%

“…Figure 10. However, as implied in [31], the range of the available back-gate bias is limited when a smaller supply voltage is used. Therefore, there are 27 different configurations in total.…”

Section: A Dpa Attacks On the Targeted Mcu With A Fixed Supply And Bmentioning

confidence: 99%

“…Second, we propose the random dynamic backgate biasing (RDBB) countermeasure, where the back-gate bias voltage is randomly altered, thus further reducing the correlation between the intermediate values and actual power consumption. A 32-bit RISC-V microcontroller, fabricated on the 65 nm silicon-on-thin-BOX (SOTB) technology [30], a previous work of ours, is used as the experimental targeted device [31]. Realistic DPA attacks on this microcontroller while it is operating on the AES-128 algorithm are conducted to verify the effectiveness of our proposed countermeasures.…”

Section: Introductionmentioning

confidence: 99%

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Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Dao

Hoang

et al. 2021

IEEE Access

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Fully depleted silicon-on-insulator (FD-SOI) technology is renowned for its back-gate bias voltage controllability. It allows devices fabricated with FD-SOI technology to be optimized for low power consumption or high performance with proper back-gate biases, depending on the required application. This article proposes using the back-gate biasing technique in novel countermeasures against power analysis attacks. Theoretical explanations are discussed, and realistic differential power analysis (DPA) attacks, targeting AES-128 encryption on a 65-nm STOB 32-bit RISC-V microcontroller, are conducted to justify the proposed idea. The experimental results show that when compared with applying no bias, applying our first proposal, which involves using forward back-gate bias, not only improves the test device performance but also enhances its resistance to DPA attacks. Moreover, vulnerability to DPA attacks is kept unchanged when a reverse back-gate bias is applied to achieve low power consumption. The DPA resistance is even more vital when combining the back-gate bias technique with a lower supply voltage. The number of power traces required to retrieve the secret key successfully increases by 14.5 times in the best case. Even better DPA resistance can be obtained when the back-gate bias of the targeted microcontroller is dynamically randomized, as suggested by our second proposal of a random dynamic back-gate bias (RDBB). When RDBB is applied, the number of power traces required to retrieve the secret key successfully significantly increases by 33.4 times. INDEX TERMS Side-channel attacks, differential power analysis, countermeasure, back-gate biasing, FD-SOI, SOTB, RISC-V.

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Section: B Test Devicementioning

confidence: 99%

Section: A Dpa Attacks On the Targeted Mcu With A Fixed Supply And Bmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Dao

Hoang

et al. 2021

IEEE Access

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“…The open-source RISC-V ISA and toolchain ecology provide the corresponding research foundation. For 32-bit fixedpoint MCU products, RISC-V ISA is classified based on modular standards, including I (Basic Instructions), M (Multiply/Divide Instructions), A (Atomic Instructions), and C (Compressed Instructions) [7,8,9,10,11,12,13,14]. At this stage, there are two types of related research in the RISC-V ISA and architecture design.…”

Section: Introductionmentioning

confidence: 99%

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

Meng

2022

IEICE Electron. Express

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With the increasing energy-efficiency requirements for the edge computing platforms, the Instruction Set Architecture (ISA) design and precision tuning techniques highlight the possibility of improving the efficiency of dedicated operations. RISC-V as an open-source instruction set shows excellent application potential. On the other hand, the modular ISA design brings elegant design ideas, and designers can pay more attention to the collaborative design of essential ISA and software libraries. To support the design of efficient precision tuned applications, this paper presents some novel architecture and software co-design based on integer and fixed-point computations. Based on a collection of RISC-V instruction custom designs for a fixed-point mathematics library, we propose an optimal decisionmaking methodology for the customized ISA design space exploration to optimize some dedicated algorithms.

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“…These processors are designed for deterministic, real-time embedded processing and microcontroller applications, and are optimized for low-cost and energy-efficiency. In addition to processors in industry, many cores are implemented in academia [ 9 , 10 , 11 , 12 , 13 , 14 ]. For example, the Pulp team from ETH and the University of Bologna has proposed several processors, including Zero-riscy, Riscy, and Ariane.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

Qiao

Gao

et al. 2021

Micromachines

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Embedded processors are widely used in various systems working on different tasks with different workloads. A more complex micro-architecture leads to better peak performance and worse power consumption. Shutting down the units designed for performance enhancement could improve energy efficiency in low-workload scenarios. In this paper, we evaluated the energy distribution in various embedded processors. According to the analysis, pipeline registers and the dynamic branch predictor, which are employed for better peak performance, have great impacts on energy efficiency. Thus, we proposed an ultra-low-power processor with variable micro-architecture. The processor is based on a 4-stage pipeline core with a Gshare branch predictor, and all units work in high-performance mode. In normal mode, the Gshare predictor is shut down and Always-Not-Taken prediction is used. In low-power mode, some of the pipeline registers are bypassed to avoid unnecessary energy dissipation and improve executing efficiency. A mode register (MR) is designed to indicate current working mode. Switching between different modes is controlled by the software. The proposed core is implemented in 40 nm technology and simulated with the traces of 17 benchmarks in Embench. The average amounts of power consumed by the respective modes are 41.7 W, 59.7 W and 71.1 W. The results show that normal mode (N-mode) and low-power mode (L-mode) consume 16.08% and 41.37% less power than high-performance mode (H-mode) on average. In best case scenarios, they could save 25.36% and 49.30% more power than H-mode. Considering the execution efficiency evaluated by instructions per cycle (IPC), the proposed processor consumes 7.78% or 51.57% less energy for each instruction than the baseline core. The area of the proposed processor is only 7.19% larger than the baseline core, and only 3.08% more power is consumed in H-mode.

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Low-power high-performance 32-bit RISC-V microcontroller on 65-nm silicon-on-thin-BOX (SOTB)

Cited by 8 publications

References 18 publications

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

Exploiting the Back-Gate Biasing Technique as a Countermeasure Against Power Analysis Attacks

A co-design method of customized ISA design space exploration and fixed-point library construction for RISC-V dedicated processor

An Ultra-Low-Power Embedded Processor with Variable Micro-Architecture

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