2021 6th International Conference for Convergence in Technology (I2CT) 2021
DOI: 10.1109/i2ct51068.2021.9417974
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Low Power High Performance 4 bit Vedic-multiplier in 32nm

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Cited by 5 publications
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“…The proposed design is also compared to some recent, closely related works in the literature, i.e., 16,17,43,44,46,47,48,49 , where 49 is an approximate multiplier-based design. It can be seen in Table 6 that our design outperforms these in terms of delay, power consumption, energy efficiency, and transistor count.…”
Section: Simulation Results and Performance Comparisonmentioning
confidence: 99%
“…The proposed design is also compared to some recent, closely related works in the literature, i.e., 16,17,43,44,46,47,48,49 , where 49 is an approximate multiplier-based design. It can be seen in Table 6 that our design outperforms these in terms of delay, power consumption, energy efficiency, and transistor count.…”
Section: Simulation Results and Performance Comparisonmentioning
confidence: 99%