Low-power, high-performance 64-bit CMOS priority encoder using static-dynamic parallel architecture

Balobas, Dimitrios; Konofaos, N.

doi:10.1109/mocast.2016.7495160

Cited by 10 publications

(5 citation statements)

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“…Despite decreasing the latency, the resource utilization rises because of the additional PRI 8 and logic gates. Another improvement from Balobas and Konofaos [6] exploited a new design of 4-bit PE (PE4) and a static-dynamic parallel priority lookahead architecture to boost the performance of PE64. However, the architectures of large-sized PEs were not mentioned.…”

Section: Previous Workmentioning

confidence: 99%

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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Abstract-In our prior study of an L-bit priority encoder (PE), a so-called one-directional-array to two-directional-array conversion method is deployed to turn an L-bit input data into an M × N-bit matrix. Following this, an N-bit PE and an M-bit PE are employed to obtain a row index and column index. From those, the highest priority bit of L-bit input data is achieved. This brief extends our previous work to construct a scalable architecture of high-performance large-sized PEs. An optimum pair of (M, N) and look-ahead signal are proposed to improve the overall PE performance significantly. The evaluation is achieved by implementing a variety of PEs whose L varies from 4-bit to 4096-bit in 180-nm CMOS technology. According to post-placeand-route simulation results, at PE size of 64 bits, 256 bits, and 2048 bits the operating frequencies reach 649 MHz, 520 MHz, and 370 MHz, which are 1.2 times, 1.5 times, and 1.4 times, as high as state-of-the-art ones.

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Section: Previous Workmentioning

confidence: 99%

A Scalable High-Performance Priority Encoder Using 1D-Array to 2D-Array Conversion

Nguyen

Pham

2017

IEEE Trans. Circuits Syst. II

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“…In the existing literature, several full-custom (i.e., transistor-level) designs for the priority resolver have been presented [5,[8][9][10][11][12][13][14][15][16][17][18]. Many of these designs [5,[8][9][10][11][12][13][14][15]18] are 2 of 12 modular, meaning that small-size priority resolver modules are combined with any extra logic to form medium-/large-size priority resolvers, and some of the designs [16,17] are non-modular meaning they are not suitable for cascading and only serve as stand-alone priority resolvers. Some of the priority resolver designs [10,12] address a specific number of primary inputs (N = 64).…”

Section: Introductionmentioning

confidence: 99%

“…Many of these designs [5,[8][9][10][11][12][13][14][15]18] are 2 of 12 modular, meaning that small-size priority resolver modules are combined with any extra logic to form medium-/large-size priority resolvers, and some of the designs [16,17] are non-modular meaning they are not suitable for cascading and only serve as stand-alone priority resolvers. Some of the priority resolver designs [10,12] address a specific number of primary inputs (N = 64). A large majority of the priority encoder designs have been implemented in or make use of domino CMOS logic [5,[9][10][11][12][13][14], while some priority encoder designs make use of dynamic CMOS logic [8,[16][17][18].…”

Section: Introductionmentioning

confidence: 99%

“…Some of the priority resolver designs [10,12] address a specific number of primary inputs (N = 64). A large majority of the priority encoder designs have been implemented in or make use of domino CMOS logic [5,[9][10][11][12][13][14], while some priority encoder designs make use of dynamic CMOS logic [8,[16][17][18]. Ref.…”

Section: Introductionmentioning

confidence: 99%

“…[15] makes use of static CMOS logic and pass-transistor logic while Refs. [12,14] makes use of static CMOS and domino CMOS logic.…”

Section: Introductionmentioning

confidence: 99%

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Gate-Level Hardware Priority Resolvers for Embedded Systems

Balasubramanian,

Maskell

2024

JLPEA

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An N-bit priority resolver having N inputs and N outputs functions as polling hardware in an embedded system, enabling access to a resource when multiple devices initiate access requests at its inputs which may be located on-chip or off-chip. Subsystems such as data buses, comparators, fixed- and floating-point arithmetic units, interconnection network routers, etc., utilize the priority resolver function. In the literature, there are many transistor-level designs for the priority resolver based on dynamic CMOS logic, some of which are modular and others are not. This article presents a novel gate-level modular design of priority resolvers that can accommodate any number of inputs and outputs. Based on our modular design architecture, small-size priority resolvers can be conveniently combined to form medium- or large-size priority resolvers along with extra logic. The proposed modular design approach helps to reduce the coding complexity compared to the conventional direct design approach and facilitates scalability. We discuss the gate-level implementation of 4-, 8-, 16-, 32-, 64-, and 128-bit priority resolvers based on the direct and modular approaches and provide a performance comparison between these based on the design metrics. According to the modular approach, different sizes of priority resolver modules were used to implement larger-size priority resolvers. For example, a 4-bit priority resolver module was used to implement 8-, 16-, 32-, 64-, and 128-bit priority resolvers in a modular fashion. We used a 28 nm CMOS standard digital cell library and Synopsys EDA tools to synthesize the priority resolvers. The estimated design metrics show that the modular approach tends to facilitate increasing reductions in delay and power-delay product (PDP) compared to the direct approach, especially as the size of the priority resolver increases. For example, a 32-bit modular priority resolver utilizing 16-bit priority resolver modules had a 39.4% reduced delay and a 23.1% reduced PDP compared to a directly implemented 32-bit priority resolver, and a 128-bit modular priority resolver utilizing 16-bit priority resolver modules had a 71.8% reduced delay and a 61.4% reduced PDP compared to a directly implemented 128-bit priority resolver.

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