Low-power high-performance double-gate fully depleted SOI circuit design

Zhang, Rongtian; Roy, Kaushik

doi:10.1109/16.998595

Cited by 23 publications

(5 citation statements)

References 16 publications

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“…Figure 6 shows the relation between f osc and V soi2p when V soi2n is fixed. It can be seen that the f osc decreases nearly linearly with V soi2p increases in the range of [-5 V, C5 V], which matches the theoretical analysis of the frequency shown in Equation (8). When the V soi2p is fixed, the larger V soi2n is the higher f osc will be.…”

Section: Resultssupporting

confidence: 79%

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DSOI—a novel structure enabling adjust circuit dynamically

et al. 2016

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A double silicon on insulator (DSOI) structure was introduced based on fully depleted SOI (FDSOI) technology. The circuit performance could be adjusted dynamically through the separate back gate electrodes applied to N-channel and P-channel devices. Based on DSOI ring oscillator (OSC), this paper focused on the theoretical analysis and electrical test of how the OSC's frequency being influenced by the back gate electrodes (soi2n, soi2p). The testing results showed that the frequency and power consumption of OSC could change nearly linearly along with the back gate bias. According to the different requirements of the circuit designers, the circuit performance could be improved by positive soi2n and negative soi2p, and the power consumption could be reduced by negative soi2n and positive soi2p. The best compromise between performance and power consumption of the circuit could be achieved by appropriate back gate biasing.

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Section: Resultssupporting

confidence: 79%

“…It can be seen that the f osc increases nearly linearly with V soi2n increases in the range of [ 5 V, C5 V]. And the larger V soi2p is the higher f osc will be when the V soi2n is fixed, which matches Equation (8). Figure 8 shows the relation between current and V soi2n when V soi2p is fixed.…”

Section: Resultssupporting

confidence: 59%

DSOI—a novel structure enabling adjust circuit dynamically

et al. 2016

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“…An analytical model of FD SOI MOSFETs has already been used by numerous authors. [17][18][19][20][21][22][23][24][25][26] Among them, several analytical models have been developed [17][18][19] on the basis of the concept of a 2D charge-sharing scheme between the gate and source/ drain regions to develop a threshold-voltage model of current-voltage (I-V) characteristics. However, the scheme of charge sharing is less or more arbitrary and oversimplified, and leads to an underestimated threshold voltage roll-off.…”

Section: Introductionmentioning

confidence: 99%

New analytical models of subthreshold surface potential and subthreshold current of fully depleted short-channel silicon-on-insulator MOSFETs with halo or pocket implantation

Wang¹

2014

Jpn. J. Appl. Phys.

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New analytical models of the subthreshold surface potential, threshold voltage and subthreshold current of fully depleted (FD) silicon on insulator MOSFETs with halo or pocket implants are presented. The subthreshold surface potential model is based on the solutions of the quasi-two-dimensional (2D) Poisson’s equation, which rigorously satisfy the boundary conditions of the continuity of the potential and electric field in the lateral direction along the channel surface of halo MOS transistors. Closed-form model equations without any fitting empirical formula correctly and efficiently generate the surface potential distribution between the source and drain regions. The drain-induced barrier lowering effect of deep-submicrometer halo MOSFETs is also addressed in the present models. On the basis of the subthreshold surface potential, analytical models of the threshold voltage and subthreshold current are also developed for deep-submicrometer halo MOSFETs. The subthreshold current model is derived using the conventional drift-diffusion current theory considering the nonuniform doping profiles of a silicon film of fully-depleted silicon-on-insulator (SOI) MOS devices with halo implants. The results obtained using the model have been compared with those obtained using the device simulation software Medici to show the validity of the proposed model, and good agreement is achieved between the two. The use of the presented models can be treated as an alternative to 2D numerical analysis and used for the design of deep-submicrometer FD SOI MOSFETs with halo or pocket implants.

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“…Since the DG MOSFET operation has been largely addressed in the literature, [3][4][5][6] the performance characteristics of small circuits based on DG MOSFET have less frequently been studied. Only few papers [7][8][9][10] report on the advantages of using DG instead of single-gate devices in complementary MOS (CMOS) inverters. However, to the best of our knowledge, a complete investigation of the impact of the DG MOSFET parameters on the inverter delay and power consumption has never been performed.…”

Section: Introductionmentioning

confidence: 99%

Impact of Geometrical and Electrical Parameters on Speed Performance Characteristics in Ultimate Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

Loussier¹,

Munteanu²,

Autran³

et al. 2008

jjap

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In this paper we present a detailed simulation analysis of the impact of geometrical (channel length, silicon film thickness and gate oxide thickness) and electrical (channel doping level and supply voltage) parameters on speed performance characteristics of double-gate metal–oxide–semiconductor field-effect transistor (MOSFET). Essential indicators of the speed performance characteristics, such as inverter delay, gate capacitances and ratio between on-state current (ION) and off-state current (IOFF), are investigated as a function of the device architecture. The study provides important guidelines for optimizing the double-gate structure in order to obtain the best compromise between power consumption and switching speed. The simulation results show that a single reduction in gate length (without modifying other device parameters) decreases the complementary MOS (CMOS) inverter delay, but strongly increases the power consumption. The reduction in channel length must be accompanied by the use of ultrathin and low doped silicon films in order to reduce the power consumption without increasing the inverter delay.

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Low-power high-performance double-gate fully depleted SOI circuit design

Cited by 23 publications

References 16 publications

DSOI—a novel structure enabling adjust circuit dynamically

DSOI—a novel structure enabling adjust circuit dynamically

New analytical models of subthreshold surface potential and subthreshold current of fully depleted short-channel silicon-on-insulator MOSFETs with halo or pocket implantation

Impact of Geometrical and Electrical Parameters on Speed Performance Characteristics in Ultimate Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors

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