Low power, high speed carbon nanotube FET based level shifters for multi-VDD Systems-On-Chips

Pasupathy, K. R.; Bindu, B.

doi:10.1016/j.mejo.2015.10.008

Cited by 11 publications

(6 citation statements)

References 26 publications

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“…CNT has a property that its energy gap (𝐸 𝑔 ) is inversely proportional to its diameter which allows to alter its band-gap by varying the diameter of CNTs. The threshold voltage ( 𝑉 𝑇𝐻 ) of the CNT-FET can be approximated as half of the CNT band-gap [13,14] as…”

Section: Cntfetmentioning

confidence: 99%

“…For critical design process interconnects modelling is necessary aspects, there are many papers which have been published by using Cu interconnects as shown in Fig. 5, here we are going to replace it with CNTFET based interconnects which has a huge potential in term of performance parameters [14,16]. PTM-MG model is developed by BSIM-CMG, for scaling multigated devices.…”

Section: Interconnectsmentioning

confidence: 99%

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Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Dadoria

Garg²,

Kushwah³

et al. 2021

Preprint

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With the quick progress in the area of digital electronics results in miniaturization of semiconductor Industries. In Deep Sub Micron regime, because of leakage current, power consumption is turn out to be a major issue; hence constant efforts are being made by the researchers for investigating the various ways to minimize this. There are various methods available for the same and out of several available methods use of Carbon Nano-tube technology is a promising way to design low power circuits efficiently. Here new techniques are introduced for the reduction of leakage power. Here in this work, comparison of the main performance parameters of Copper on chip nano-interconnect with CNTFET has been done. We have measured the impact of ION and IOFF current by applying Process variation in CU and CNT- Interconnects with the variation of Tubes at 32nm technology and analysed the performance of the digital circuits with scaling of technology. The different kind of simulation outcomes indicates that by applying 10% of deviation from normal value in different device characteristics parameters such as Length of Gate (LTube) of the Tube, Width (WTube) of the Tube, Threshold Voltage (Vth) of the Tube, Thickness (tot) of Tube and Source & Drain Doping concentration with Cu and CNTFET interconnects for NFET and PFET with the variation of tubes from 1 to 16. All the experimental outcomes are achieved by using HSPICE simulator using SPICE model of CU and CNT at27oC temperature by using 32nm Berkley Predictive Technology module.

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Section: Cntfetmentioning

confidence: 99%

Section: Interconnectsmentioning

confidence: 99%

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Dadoria

Garg²,

Kushwah³

et al. 2021

Preprint

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“…(16,0) 1.251 0.348 (19,0) 1.486 0.293 (22,0) 1.720 0. 253 (25,0) 1.955 0.223 Source: Pasupathy and Bindu (2015) Figure 6 Basic inverter as repeater…”

Section: Performance Benchmarking Of Test-bench Structurementioning

confidence: 99%

Designing dual-chirality and multi-V_trepeaters for performance optimization of 32 nm interconnects

Khursheed

Khare

2020

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Purpose This paper is an unprecedented effort to resolve the performance issue of very large scale integrated circuits (VLSI) interconnects encountered because of the scaling of device dimensions. Repeater interpolation technique is an effective approach for enhancing speed of interconnect network. Proposed buffers as repeater are modeled by using dual chirality multi-Vt technology to reduce delay besides mitigating average power consumption. Interconnects modeled with carbon nanotube (CNT) technology are compared with copper interconnect for various lengths. Buffer circuits are designed with both CNT and metal oxide semiconductor technology for comparison by using various combination of (CMOSFET repeater-Cu interconnect) and (CNTFET repeater-CNT interconnect). Compared to conventional buffer, ProposedBuffer1 saves dynamic power by 84.86%, leakage power by 88% and offers reduction in delay by 72%. ProposedBuffer2 brings about dynamic power saving of 99.94%, leakage power saving of 93%, but causes delay penalty. Simulation using Stanford SPICE model for CNT and silicon-field effective transistor berkeley short-channel IGFET Model4 (BSIM4) predictive technology model (PTM) for MOS is done in H simulation program with integrated circuit emphasis for 32 nm. Design/methodology/approach Usually, the dynamic power consumption dominates the total power, while the leakage power has a negligible effect. But with the scaling of device technology, leakage power has become one of the important factors of consideration in low power design techniques. Various strategies are explored to suppress the leakage power in standby mode. The adoption of a multi-threshold design strategy is an effective approach to improve the performance of buffer circuits without compromising on the delay and area overhead. Unlike MOS technology, to implement multi-Vt transistors in case of CNT technology is quite easy. It can be achieved by varying diameter of carbon nanotubes using chirality control. Findings An unprecedented approach is taken for optimizing the delay and power dissipation and hence drastically reducing energy consumption by keeping proper harmony between wire technology and repeater-buffer technology. This paper proposes two novel ultra-low power buffers (PB1 and PB2) as repeaters for high-speed interconnect applications in portable devices. PB1 buffer implemented with high-speed CML technique nested with multi-threshold (Vt) technology sleep transistor so as to improve the speed along with a reduction in standby power consumption. PB2 is judicially implemented by inserting separable sized, dual chirality P type carbon nanotube field effective transistors. The HSpice simulation results justify the correctness of schemes. Originality/value Result analysis points out that compared to conventional Cu interconnect, the CNT interconnects paired with Proposed CNTFET buffer designs are more energy efficient. PB1 saves dynamic power by 84.86%, reduces propagation delay by 72% and leakage power consumption by 88%. PB2 brings about dynamic power saving of 99.4%, leakage power saving of 93%, with improvement in speed by 52%. This is mainly because of the fact that CNT interconnect offers low resistance and CNTFET drivers have high mobility and ballistic mode of operation.

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“…Furthermore, the chirality vector (m, n) determines their conductor or semiconductor behavior. SWCNTs, particularly adept at high-speed carrier transport and nanostructure construction, find utility in various VLSI schemes, including combinational logic gates, counters, and multiplexers [13][14][15][16]. These unique properties stem from CNTs' cylindrical nanostructure, comprising graphene sheets rolled into tubes with diameters as small as a few nanometers and lengths reaching several millimeters [17].…”

Section: Introductionmentioning

confidence: 99%

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

Maqbool,

Sharma

2024

Eng. Res. Express

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Device scaling is a pivotal aspect in the field of electronics, aimed at enhancing the performance of integrated circuits (ICs) by reducing the dimensions of transistors. The device scaling presents the short channel effects (SCEs) in the nanoscale regime. To address the SCEs, nanometer IC designers have turned to the carbon nanotube field-effect transistor (CNTFET) technology, which offers unique properties and mitigates the challenges associated with transistor scaling. In this research work, a leakage reduction technique known as the input-dependent (INDEP) method is suggested to tackle the leakage current issue at the nanoscale regime using CNTFET technology. The INDEP method involves the incorporation of two additional transistors within the logic circuit. To evaluate the efficacy of the INDEP method, a CNTFET-based 7-stage inverter chain is meticulously designed at 32 nm CNTFET technology node. Subsequent comparative analysis against alternative designs is conducted, assessing performance metrics such as power dissipation, delay, and power delay product (PDP). The suggested INDEP method reduces power dissipation by 83.75% and improves PDP by 78.44%. Furthermore, the study delves into the impact of process, voltage, and temperature (PVT) variations. Additionally, the investigation explores the influence of parameters such as the number of carbon nanotubes, temperature, supply voltage, and chiral indices on the performance of the 7-stage inverter chain. The simulation results demonstrate that the CNTFET-based INDEP technique yields promising outcomes, characterized by low power dissipation, precise output, and minimal uncertainty across all evaluated metrics.

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Low power, high speed carbon nanotube FET based level shifters for multi-VDD Systems-On-Chips

Cited by 11 publications

References 26 publications

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Designing dual-chirality and multi-V_trepeaters for performance optimization of 32 nm interconnects

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

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Low power, high speed carbon nanotube FET based level shifters for multi-VDD Systems-On-Chips

Cited by 11 publications

References 26 publications

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Design and Analysis of CNTFET based VLSI Interconnects by Using PVT Variation

Designing dual-chirality and multi-Vtrepeaters for performance optimization of 32 nm interconnects

Circuits implementations using carbon nanotube field-effect transistor nanotechnology

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Designing dual-chirality and multi-V_trepeaters for performance optimization of 32 nm interconnects