Low-Power High-Speed CNTFET-based 1-bit Comparator Design using CCT and STT Techniques

Rajora, Ricky; Sharma, Kulbhushan; Gupta, Lipika; Sachdeva, Ashish; Sharma, Avinash

doi:10.1109/icears56392.2023.10084990

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Cited by 7 publications

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Static Approximate Modified Mirror—Full Adder for High Speed and Low Power Operations Using 32 nm CNTFET Technology

Juneja,

Elangovan,

Sharma

2024

Int J Numerical Modelling

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The error tolerance nature of the digital multimedia applications enables the implementation of approximate digital circuits to achieve the benefits of high speed of operation and low power consumption. This paper proposes a static approximate modified mirror full adder (SAMM‐FA) circuit designed using logic level approximation to reduce the number of transistors in the circuit. Owing to the balanced electrical characteristics, better stability and higher on‐current to off‐current ratio (Ion/Ioff), 32 nm carbon nanotube field effect transistor (CNTFET) technology has been used for implementing the proposed circuit in the Cadence Virtuoso tool. Featuring only 10 transistors and operating at a supply voltage of 0.5 V, the proposed SAMM‐FA has a low power dissipation of just 4.14 nW, and propagation delay of just 3.82 ps. The power delay product and energy delay product figure of merits of the proposed circuit are found to be excellent when compared with the contemporary designs.

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