Low-Power Highly Robust Resistance-to-Period Converter

Abstract

This paper presents a novel structure of Resistance- to-Period (R-T) Converter highly robust to supply and temperature variations. Robustness is achieved by using the ratiometric approach so that complex circuits or high accuracy voltage references are not necessary. To prove the proposed architecture of R-T converter, a prototype was implemented in a 0.18 μm CMOS process with a single supply voltage of 1.8 V and without any stable reference voltage. Experimental results show a maximum ±1.5% output signal variation for ±10% supply voltage variation and in a 3–95 °C temperature range.

Low‐power temperature‐independent CMOS measurement circuits for resistive gas sensors

“…Equation (9) shows that the output period could be affected by temperature through voltage references V REF 1 , V L , and V H ; the current reference I 0 ; and passive components R T and C. This is the reason why temperature stable voltage and current references are relevant to the overall behavior of the circuit. C is constructed with two different capacitor technologies in parallel whose temperature constants are opposite.…”

“…10 This cancellation methodology cannot be applied to R T since a resistance of 40 MΩ is needed and this value can only be achieved occupying a reasonable amount of area with a high density polysilicon resistor, which has no counterpart with a similar density and opposite thermal coefficient. However, by looking at (9), it can be seen that temperature effects in τ due to R T can be reduced if V REF 11 varies with a similar temperature coefficient. Since R T has a negative temperature coefficient, V REF 11 is given a negative coefficient too.…”

“…The behavior of the switches controlling if either I 1 charges or I 0 discharges the capacitor is the same as in Design #1. Thus, the output period depends upon I 0 and I 1 in the same way as in (9), and replacing I 1 with its expression:…”

“…The output period is where it can be seen that the output period is actually proportional to . A single comparator was used instead of two since this approach consumes less power and the comparator's offset does not affect 9 . A2 and B1 schematics are shown at the bottom of Figure 3.…”