Low-Power Image-Segmentation VLSI Design based on a Pixel-Block Scanning Architecture

Okazaki, Keita; Awane, Kazutoshi; Nagaoka, Naomi; Sugahara, Tohru; Koide, Tetsushi; Mattausch, H. J.

doi:10.7567/ssdm.2008.p-5-2

Cited by 1 publication

(3 citation statements)

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“…We implemented the 2D architecture with an FPGA, and confirmed its advantages over a 1D scanning architecture [6].…”

Section: Introductionmentioning

confidence: 56%

“…The 2D architecture is further implementing two additional optimization techniques, namely the boundary scan only technique [6] and the continued block-internal region growing technique [6]. Fig.…”

Section: D Pixel-block Image Scanning Segmentationmentioning

confidence: 99%

“…We have previously reported a onedimensional scanning method for realizing region-growingbased image segmentation [5] and its efficient LSI implementation [6]. This previously reported architecture can achieve low power and small area consumption, while maintaining real-time processing capability.…”

Section: Introductionmentioning

confidence: 99%

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Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Koide

Kimura

Sugahara

et al. 2010

2010 First International Conference on Networking and Computing

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We report a two-dimensional (2D) pixel block scanning architecture for image segmentation by segment growing. This architecture can optimize processing speed, power consumption, and circuit area by modifying size and shape of the pixel block. Real-time processing can be maintained by using additional the two important techniques of (i) boundary-scan of the grown segment only, (ii) continued block-internal segment growing. We analyze and optimize the size and shape trade-offs for the pixel block, and evaluate the proposed architecture by an FPGA. Altogether, the investigated architecture concepts reduce the area-time product by 52.3 % in comparison to a previously reported one-dimensional (1D) scanning architecture.

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“…We implemented the 2D architecture with an FPGA, and confirmed its advantages over a 1D scanning architecture [6].…”

Section: Introductionmentioning

confidence: 56%

Section: D Pixel-block Image Scanning Segmentationmentioning

confidence: 99%

See 1 more Smart Citation

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Koide

Kimura

Sugahara

et al. 2010

2010 First International Conference on Networking and Computing

Self Cite

View full text Add to dashboard Cite

show abstract

Low-Power Image-Segmentation VLSI Design based on a Pixel-Block Scanning Architecture

Cited by 1 publication

References 0 publications

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

Architecture and FPGA-Implementation of Scalable Picture Segmentation by 2D Scanning with Flexible Pixel-Block Size

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