Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine

Pathak, Rakshit; Dash, Saurav; Mukhopadhyay, Anand Kumar; Basu, Arindam; Sharad, Mrigank

doi:10.1109/isvlsi.2017.54

Cited by 8 publications

(5 citation statements)

References 17 publications

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“…In view of the above, a number of analog building blocks, powered with supply voltages (VDD) as low as 0.5V are required including silicon neuron, WTA, operational amplifier, voltage comparator, synapse, and many others. Therefore, an interesting challenge that circuit and system designers will deal with could be implementing ultralowpower and ultralow-voltage spiking neural networks with the capability of interacting with real signals [36][37][38]. However, the designed learning module with a supply voltage of 0.5V can only be used in CMOS-based neural networks.…”

Section: Simulation Resultsmentioning

confidence: 99%

Low-Voltage Implementation of Neuromorphic Circuits for a Spike-Based Learning Control Module

Akbari

Tang²

2022

IEEE Access

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Recent brain emulation engines have been configured using thousands of neurons and billions of synapses. These components make a significant impact on the whole system in terms of power consumption and silicon area. In this work, several upgraded neuromorphic circuits are used to configure an efficient and compact spike-based learning control module that is capable of operating under ultralowvoltage supplies offering a low energy consumption per spike. In this way, a conductance-based silicon neuron is developed using the simplest highly efficient analog circuits. Moreover, an upgraded winner-takeall (WTA) circuit is used to form a low-voltage multi-threshold current comparator to determine whether to increase or decrease the synaptic weight. Other components such as low-speed amplifier, differential pair integrator (DPI)-based synapse, and weight update controller are designed such that they properly operate under a 0.5V supply voltage. Simulation results in TSMC 0.18 µm CMOS process show an energy consumption of 2.5 pJ for the upgraded learning control module, while its stop-learning mechanism improves the performance of the system by avoiding overfitting.

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Section: Simulation Resultsmentioning

confidence: 99%

Low-Voltage Implementation of Neuromorphic Circuits for a Spike-Based Learning Control Module

Akbari

Tang²

2022

IEEE Access

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“…There are also supervised variants of SNNs proposed for spike sorting [83,88]. In these works, the detected spike is first rate-encoded, meaning that the analog waveform is converted to a binary spike train whose frequency is proportional to the magnitude of the analog signal.…”

Section: Spiking Neural Networkmentioning

confidence: 99%

Spike sorting algorithms and their efficient hardware implementation: a comprehensive survey

et al. 2023

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Objective: Spike sorting is a set of techniques used to analyze extracellular neural recordings, attributing individual spikes to individual neurons. This field has gained significant interest in neuroscience due to advances in implantable microelectrode arrays, capable of recording thousands of neurons simultaneously. High-density electrodes, combined with efficient and accurate spike sorting systems, are essential for variousapplications, including Brain Machine Interfaces (BMI), experimental neural prosthetics, real-time neurological disorder monitoring, and neuroscience research. However, given the resource constraints of modern applications, relying solely on algorithmic innovation is not enough. Instead, a co-optimization approach that combines hardware and spike sorting algorithms must be taken to develop neural recording systems suitable for resource-constrained environments, such as wearable devices and BMIs. This co-design requires careful consideration when selecting appropriate spike-sorting algorithms that match specific hardware and use cases. Approach: We investigated the recent literature on spike sorting, both in terms of hardware advancements and algorithms innovations. Moreover, we dedicated special attention to identifying suitable algorithm-hardware combinations, and their respective real-world applicabilities. Main Results: In this review, we first examined the current progress in algorithms, and described the recent departure from the conventional ”3-step” algorithms in favor of more advanced template matching or machine-learning-based techniques. Next, we explored innovative hardware options, including Application-Specific Integrated Circuits (ASICs), Field-Programmable Gate Arrays (FPGAs), and In-Memory Computing Devices (IMCs). Additionally, the challenges and future opportunities for spike sorting are discussed.Significance: This comprehensive review systematically summarizes the latest spike sorting techniques and demonstrates how they enable researchers to overcome traditional obstacles and unlock novel applications. Our goal is for this work to serve as a roadmap for future researchers seeking to identify the most appropriate spike sorting implementations for various experimental settings. By doing so, we aim to facilitate the advancement of this exciting field and promote the development of innovative solutions that drive progress in neural engineeringresearch.

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“…It consists of a differentiator, comparator, counters, decoder, digital to analog converters (DACs), current-controlled oscillators (CCOs), and multi-bit RCN as the major sub-modules. Low-power implementation of the front-end amplifier and the CCO has been previously studied [31,32]. We used a CCO with three inverter stages for a frequency range of 1 kHz to 650 kHz, as shown in figure 13(b).…”

Section: Mixed Implementation Of Feature Extractionmentioning

confidence: 99%

Acoustic scene analysis using analog spiking neural network

Mukhopadhyay

Naligala

Duggisetty

et al. 2022

Neuromorph. Comput. Eng.

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Sensor nodes in a wireless sensor network (WSN) for security surveillance applications should preferably be small, energy-efficient, and inexpensive with in-sensor computational abilities. An appropriate data processing scheme in the sensor node reduces the power dissipation of the transceiver through the compression of information to be communicated. This study attempted a simulation-based analysis of human footstep sound classification in natural surroundings using simple time-domain features. The spiking neural network (SNN), a computationally low-weight classifier derived from an artificial neural network (ANN), was used to classify acoustic sounds. The SNN and required feature extraction schemes are amenable to low-power subthreshold analog implementation. The results show that all analog implementations of the proposed SNN scheme achieve significant power savings over the digital implementation of the same computing scheme and other conventional digital architectures using frequency-domain feature extraction and ANN-based classification. The algorithm is tolerant of the impact of process variations, which are inevitable in analog design, owing to the approximate nature of the data processing involved in such applications. Although SNN provides low-power operation at the algorithm level, ANN to SNN conversion leads to an unavoidable loss of classification accuracy of ~5%. We exploited the low-power operation of the analog processing SNN module by applying redundancy and majority voting, which improved the classification accuracy, taking it close to the ANN model.

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Low Power Implantable Spike Sorting Scheme Based on Neuromorphic Classifier with Supervised Training Engine

Cited by 8 publications

References 17 publications

Low-Voltage Implementation of Neuromorphic Circuits for a Spike-Based Learning Control Module

Low-Voltage Implementation of Neuromorphic Circuits for a Spike-Based Learning Control Module

Spike sorting algorithms and their efficient hardware implementation: a comprehensive survey

Acoustic scene analysis using analog spiking neural network

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