Low Power Implementation of 32-Bit RISC Processor with Pipelining

Mangalwedhe, Sneha; Kulkarni, Roopa; Kulkarni, S. Y.

doi:10.1007/978-981-10-8234-4_27

Cited by 6 publications

(2 citation statements)

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“…RISC processors are efficient in various ways compared to CISC processors as they consume less power, execute faster as the number of instructions is less andhas simplified addressing modes with simpler designs etc. [4][5][6][7][8][9].…”

Section: Introductionmentioning

confidence: 99%

Untitled

2019

VLSICS

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Pipelining is a technique that exploits parallelism, among the instructions in a sequential instruction stream to get increased throughput, and it lessens the total time to complete the work. . The major objective of this architecture is to design a low power high performance structure which fulfils all the requirements of the design. The critical factors like power, frequency, area, propagation delay are analysed using Spartan 3E XC3E 1600e device with Xilinx tool. In this paper, the 32-bit MIPS RISC processor is used in 6-stage pipelining to optimize the critical performance factors. The fundamental functional blocks of the processor include Input/Output blocks, configurable logic blocks, Block RAM, and Digital clock Manager and each block permits to connect to multiple sources for the routing. The Auxiliary units enhance the performance of the processor. The comparative study elevates the designed model in terms of Area, Power and Frequency. MATLAB2D/3D graphs represents the relationship among various parameters of this pipelining. In this pipeline model, it consumes very less power (0.129 W),path delay (11.180 ns) and low LUT utilization (421). Similarly, the proposed model achieves better frequency increase (285.583 Mhz.), which obtained better results compared to other models. MATLAB, SPARTAN3E, MIPS RISC processor, Xilinx, Digital Clock Manager. KEYWORDS

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Section: Introductionmentioning

confidence: 99%

Untitled

2019

VLSICS

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“…Reduced Instruction Set Computer (RISC) is smart computer architecture; it uses the most required 20% of the instructions; makes the pipelining much faster; and reduces the power consumption [5]. The first successful and classical MIPS RISC Processor contains 32-bit, 5-stage Pipelining with load and store memory access instructions [6]. RISC Processor nurtures the complexity at software level rather than at hardware level [7].…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of 6-Stage 64-bit MIPS Pipelined Architecture

Indira¹,

Kamaraju²

2019

IJEAT

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Pipelining is the concept of overlapping of multiple instructions to perform their operations to optimize the time and ability of hardware units. This paper presents the design and implementation of 6 stage pipelined architecture for High performance 64-bit Microprocessor without Interlocked Pipeline Stages (MIPS) based Reduced Instruction set computing (RISC) processor. In this work, combining efforts of pre-fetching unit, forwarding unit, Branch and Jump predicting unit, Hazard unit are used to reduce the hazards. Low power unit is used to minimize the power. Cache Memories, other devices and especially balancing pipeline stages optimize the Speed in this work. DDR4 SDRAM (Double Data Rate type4 Synchronous Dynamic Random Access Memory) controller is employed in this pipeline to achieve high-speed data transfers and to manage the entire system efficiently. Low power, Low delay Flip flops are used in pipeline registers that implicitly enhance the performance of the system. The proposed method provides better results compared to the existing models. The simulation and synthesis results of the proposed Architecture are evaluated by Xilinx 14.7 software and supporting graphs are plotted through MATLAB tool

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