Low power LDPC decoder with efficient stopping scheme for undecodable blocks

Shirani-Mehr, Houshmand; Baas, Bevan M.

doi:10.1109/iscas.2011.5937929

Cited by 9 publications

(8 citation statements)

References 9 publications

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“…However, MSESC is affected only by the number of bits f (taken in account by T 2) and not by the total number of bits: its effectiveness is consequently guaranteed for all quantizations. The [17] ESC and EMESC show similar performance, with two saved iterations at zero SNR, while CMM performs much better at low SNR. A large number of saved iterations can be observed for MSESC and [18] ESC.…”

Section: Msesc Performancementioning

confidence: 84%

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Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

2014

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International audienceLow-density-parity-check codes decoding relies on powerful iterative algorithms, whose implementation is often expensive in terms of complexity and power consumption. Several early stopping criteria (ESCs) have been proposed to reduce the number of iterations performed by a decoder with no (or limited) degradation of error correction performance. However, most of the existing ESCs have considered a reduced set of system parameters for validation and often have ignored the impacts related to a real hardware implementation. This study proposes a novel multi-standard early stopping criterion (MSESC) able to adapt dynamically to changes of code parameters, quantisation and channel conditions. A dedicated hardware architecture is devised and integrated in a multi-standard decoder, and compared with existing techniques. Post-layout results of the proposed MSESC show a small area increment (+1.3%) and a large decrement of the average energy consumption (up to 87.2%) with respect to the same decoder implemented with no ESC. Moreover, it is shown that MSESC offers an energy consumption reduction with respect to the state-of-the-art ESCs ranging from 4% [at high signal-to-noise ratio (SNR)] to 16% (at low SNR)

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Section: Msesc Performancementioning

confidence: 84%

“…Incorporation of early stopping criteria (ESC) in an iterative LDPC decoder enables energy saving by limiting the average number of decoding iterations [15][16][17][18][19]. In this approach, the evolution of a certain metric is analysed over the iterations and a proper stopping rule is set.…”

Section: Introductionmentioning

confidence: 99%

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

2014

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“…This low utilization is due to the fact that the two minimum values and the corresponding index for each check node should be generated and propagated throughout the entire decoder, resulting in complex interconnects. Consequently, the SRTA was used in [11] and [12] in order to reduce the routing complexity of the LDPC decoder, where the paritycheck matrix is divided into several sub-matrices in a columnwise form, and only local minimum values for each sub-matrix are found and compared with a pre-determined threshold. As a result, the global-wire interconnects can be significantly reduced and a high utilization can be achieved for the decoder presented in [12].…”

Section: Hardware Implementation a Realization Resultsmentioning

confidence: 99%

Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

Lee

Cheng

Ueng

2014

2014 8th International Symposium on Turbo Codes and Iterative Information Processing (ISTC)

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In order to simplify the check node operation of the low-density parity-check (LDPC) decoders, this paper presents a Normalized Probabilistic Min-Sum Algorithm (NPMSA), where the second minimum value is replaced by a probabilistic second minimum value. For NPMSA, the number of required comparisons can be reduced to about half compared to that of the conventional Normalized Min-Sum Algorithm (NMSA). It is shown that the simplification only introduces negligible impact on the bit-error rate performance, especially for codes with a high check node degree. When the proposed NPMSA is applied to the (2048, 1723) RS-LDPC code, the degradation in the error-rate performance is only about 0.05 dB. The hardware implementation shows that a throughput of 45.42 Gbps can be achieved using the proposed NPMSA.

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“…When decoding failure is anticipated, the error correction procedure is terminated early, thereby effectively reducing the decoding complexity. To the best of our knowledge, a number of early termination techniques for other error correction codes such as low-density parity check (LDPC) or turbo codes have been introduced [28][29][30][31][32][33][34][35]. However, there have been no studies of early termination techniques for TPCs.…”

Section: Proposed Syndrome-based Decoding Algorithmmentioning

confidence: 99%

An advanced low-complexity decoding algorithm for turbo product codes based on the syndrome

Yoon

Ahn

Heo

2020

J Wireless Com Network

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This paper introduces two effective techniques to reduce the decoding complexity of turbo product codes (TPC) that use extended Hamming codes as component codes. We first propose an advanced hard-input soft-output (HISO) decoding algorithm, which is applicable if an estimated syndrome stands for double-error. In conventional soft-input soft-output (SISO) decoding algorithms, 2 p (p: the number of least reliable bits) number of hard decision decoding (HDD) operations are performed to correct errors. However, only a single HDD is required in the proposed algorithm. Therefore, it is able to lower the decoding complexity. In addition, we propose an early termination technique for undecodable blocks. The proposed early termination is based on the difference in the ratios of double-error syndrome detection between two consecutive half-iterations. Through this early termination, the average iteration number is effectively lowered, which also leads to reducing the overall decoding complexity. Simulation results show that the computational complexity of TPC decoding is significantly reduced via the proposed techniques, and the error correction performance remains nearly the same in comparison with that of conventional methods.

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Low power LDPC decoder with efficient stopping scheme for undecodable blocks

Cited by 9 publications

References 9 publications

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

Energy‐efficient multi‐standard early stopping criterion for low‐density‐parity‐check iterative decoding

Hardware-friendly Probabilistic Min-Sum algorithm for fully-parallel LDPC decoders

An advanced low-complexity decoding algorithm for turbo product codes based on the syndrome

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