Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

Askhedkar, Anuja; Agrawal, Girdharilal

doi:10.1016/j.jksues.2017.08.001

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Proposed Modification In Ppa1

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Cited by 3 publications

(1 citation statement)

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“…But the two nmos transistors N1 and N2 will be in OFF state. This is supposed to pull down the output to zero, but due to the poor transmission characteristics of the pmos, the output will be |Vtp| [27][28][29][30]. When AB = 01, P1 will be ON, P2 will be OFF, N1 will be in ON condition and N2 will be in OFF state.…”

Section: Proposed Modification In Ppamentioning

confidence: 99%

Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Rakesh¹,

Grace²

2020

IJCDS

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Section: Proposed Modification In Ppamentioning

confidence: 99%

Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Rakesh¹,

Grace²

2020

IJCDS

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Power Minimization Twisted Ring Counter Design Using Power Gating Technique

Jayapraba,

Keerthi,

Vidya

et al. 2024

Lecture Notes in Electrical Engineering

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Design of High-Speed Low Power Computational Blocks for DSP Processors

Manga¹,

Tallapragada²,

Kumar³

et al. 2021

revistageintec

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In today’s deep submicron VLSI (Very Large-Scale Integration) Integrated Circuits, power optimization and speed play a very important role. This importance for low power has initiated the designs where power dissipation is equally important as performance and area. Power reduction and power management are the key challenges in the design of circuits down to 100nm. For power optimization, there are several techniques and extension designs are applied in the literature. In real time Digital Signal Processing applications, multiplication and accumulation are significant operations. The primary performance criteria for these signal processing operations are speed and power consumption. To lower the power consumption, there are techniques like Multi threshold (Multi-Vth), Dula-Vth etc. Among those, a technique known as GDI (Gate diffusion Input) is used which allows reduction in power, delay and area of digital circuits, while maintaining low complexity of logic design. In this paper, various signal processing blocks like parallel-prefix adder, Braun multiplier and a Barrel shifter are designed using GDI (Gate diffusion Input) technique and compared with conventional CMOS (Complementary Metal Oxide Semiconductor) based designs in terms of delay and speed. The designs are simulated using Cadence Virtuoso 45nm technology. The Simulation results shows that GDI based designs consume less power and delay also reduced compared to CMOS based designs.

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Low Power, Low Area Digital Modulators using Gate Diffusion Input Technique

Cited by 3 publications

References 20 publications

Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Power Efficient Multiply Accumulate Architectures using Modified Parallel Prefix Adders for Low Power Applications

Power Minimization Twisted Ring Counter Design Using Power Gating Technique

Design of High-Speed Low Power Computational Blocks for DSP Processors

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