Low-Power Low-Complexity FM-UWB Transmitter in 130nm CMOS for WBAN Applications

Fathy, Amr A; Said, Muhammad Haitham; Mohamed, Hagar Amir; Rasmy, Sandra Safwat; Ellaithy, Dina M.

doi:10.1109/icces51560.2020.9334586

Cited by 4 publications

(1 citation statement)

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“…The development of electronic technologies that can interact with bio-tissues and organs at the micro and nanoscales, as well as a growing understanding of many aspects of the human nervous system, has been essential for the conception and subsequent development of these devices. A large number of small wireless electronic devices (e.g., sensors, smart gastric/cardiac pacemakers, cochlear implants, and implantable cardioverters defibrillators, as well as deep brain, nerve and bone stimulators) have been implanted into patients worldwide [3,4] due to recent development in electronics especially the smaller size and lower energy demands as shown in Fig. 1.…”

Section: Introductionmentioning

confidence: 99%

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Ellaithy

2024

Journal of Electrical Systems and Inf Technol

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Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

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Section: Introductionmentioning

confidence: 99%