Low power low jitter phase locked loop for high speed clock generation

Singh, Gauri Shankar; Singh, Devesh; Moorthi, S.

doi:10.1109/primeasia.2012.6458652

Cited by 13 publications

(1 citation statement)

References 4 publications

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“…Then, the practical applicability of the polyphase-clocked architecture is then limited to small number of phases. It is noted that sophisticated techniques can indeed be used to interleave many ADC operations leading to high throughput albeit at the cost of using on-chip calibration techniques to address challenges with clock synchrony and phase jitter [55,56]. The proposed system uses a single-phase clock.…”

Section: Digital Enginementioning

confidence: 99%

Wide‐band aperture array using a four‐channel manifold‐type planar multiplexer and digital 2‐D IIR filterbank

Sengupta

Madanayake

Gómez‐García

et al. 2016

Circuit Theory & Apps

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SUMMARYEmerging wide-band communications and spectrum-sensing systems demand support for multiple electronically scanned beams while maintaining a frequency independent, constant far-field beam width. Realizing existing phased-array technology on a digital scale is computationally intensive. Moreover, digitizing wide-band signals at Nyquist rate requires complex high-speed analog-to-digital converters (ADCs), which is challenging for real developments driven by the current ADC technology. A low-complexity alternative proposed in this paper is the use of radio-frequency (RF) channelizers for spectrum division followed by sub-sampling of the RF sub-bands, which results in extensive reduction of the necessary ADC operative frequency. The RF-channelized array signals are directionally filtered using 2-D digital filterbanks. This mixed-domain RF/digital aperture array allows sub-sampling, without utilizing multi-rate 2-D systolic arrays, which are difficult to realize in practice. Simulated examples showing 14-19 dB of rejection of wide-band interference and noise for a processed bandwidth of 1.6 GHz are demonstrated. The sampling rate is 400 MHz. The proposed VLSI hardware uses a single-phase clock signal of 400 MHz. Prototype hardware realizations and measurement using 65-nm Xilinx field-programmable gate arrays, as well as Cadence RTL synthesis results including gate counts, area-time complexity, and dynamic power consumption for a 45-nm CMOS circuit operating at B DC = 1.1 V, are presented.

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Section: Digital Enginementioning

confidence: 99%