Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

Mukherjee, Paramita; Chattopadhyay, Santanu

doi:10.1016/j.vlsi.2017.02.010

Cited by 7 publications

(6 citation statements)

References 30 publications

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“…A Nirgam simulator is used to evaluate the proposed algorithm whose capabilities are listed in Table 3 [5]. Nirgam is a scalable, modular simulator based on the system C hardware description language, enabling various options at every stage of NoC design, including topology, switching methods, virtual channels, buffer parameters, and tested routing mechanisms.…”

Section: Evaluation and Simulation Environmentmentioning

confidence: 99%

“…In other words, the interval between injection of header flit in the network of the source node and receiving one flit sequence in the destination node is packet latency. In Equation (20), K is the total number of delivered messages in the destination node, and Li is the delay of the i th message [5]:…”

Section: Evaluated Parametersmentioning

confidence: 99%

“…The result was so satisfactory that after a short time, the systems consisted of several sections that ran on a board, relocated in a single chip. This architecture of processor construction became popular as system on chip or SoC [3][4][5]. However, SoC had issues emerging over time.…”

Section: Introductionmentioning

confidence: 99%

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A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on Chip

et al. 2022

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Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have been able to handle the communication between processing cores, inspired by computer networks. Efficient nonstop routing is one of the most significant applications of NOC. In fact, there are different routes to reach from one node to another node in these networks; therefore, there should be a function that can help to build the best route to reach the destination. In the current study, a new hybrid algorithm scored regional congestion-aware and neighbors-on-path (ScRN) is introduced to choose better output channel and thus improve NOC performance. Having utilized the ScRN algorithm, first an analyzer is used to inspect the traffic packets, and then the NoC traffic locality or nonlocality is determined based on the number of the hops. Finally, if the traffic is local, a scoring technique will choose better output channel; however, if the traffic is nonlocal, the best output channel will be chosen based on a particular parameter introduced here as well as the system status using NoP or RCA selection functions. In the end, via Nirgam simulation, the proposed approach was assessed in traffic scenarios through various selection functions. The simulation results showed that the solution was more successful in terms of delay time, throughput, and energy consumption in comparison to other solutions. It showed a reduction of 38% in packet latency, and the throughput increased by 20%. By considering these two parameters, energy consumption decreased by 10% on average.

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Section: Evaluation and Simulation Environmentmentioning

confidence: 99%

Section: Evaluated Parametersmentioning

confidence: 99%

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A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on Chip

et al. 2022

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“…This design is susceptible to use large queues. In application-specific NoC [22], both positions of the routers and the route for each communication trace of the application can be adjusted to suit the requirements. However, it increases the complexity of the system by using a power calculator.…”

Section: Related Workmentioning

confidence: 99%

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

2021

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Switch Allocation (SA) holds a critical stage in Network-on-Chip (NoC) routers, its performance gets affected adversely due to Head-of-Line (HoL) blocking. In traditionally used Input-Queued Routers (IQR), packets are arranged in a particular order in each Virtual Channel (VC). This implementation is vulnerable to HoL blocking, as the switch allocator can allocate only those packets which are available at the head in a VC. In this paper, Swapped Buffer (SB) Router architecture is proposed to schedule packets in input buffers by using SB registers. The VCs are designed as SBs, this allows the packets stored in SB registers along with the head packet of VC to participate in SA. The concept of the SB register minimizes the conflicts in SA and thus reduces HoL blocking, therefore improves the performance of NoC. This paper proposes a priority mechanism to prioritize the non-head packets as compared to head packets in case of conflict between them. Two methods have been proposed in this paper, to enhance the performance of the NoC router. First, a VC allocation technique is proposed to optimize the order of packets in the input buffer. Next, SB-Router is combined with the Fill VC allocation technique to further enhance the performance of NoC routers. The performance of the proposed router is evaluated and the experimental results indicate that our design achieves latency improvement of 68.75% over (Time-Series) TS-Router for uniform traffic at the injection rate of 0.42 flits/cycle for a 64 node mesh network with moderate power consumption and area usage. The performance improvement in packet latency for traces from Princeton Application Repository for Shared-Memory Computers (PARSEC) has also been evaluated. With the achieved reduction in latency, the proposed method has the potential to serve high-speed operations while mapping different applications on multiple core architectures.

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“…Heterogeneous Multiprocessor Systems-on-Chips (MPSoCs) are widely accepted as a solution for future embedded systems (Leupers et al, 2017). With the increase of the number of processing elements in Systems-on-Chip (SoCs), it becomes very difficult to continue with the traditional non-scalable bus-based communication systems (Mukherjee & Chattopadhyay, 2017). The Network on chip (NoC) (Benini &Micheli, 2002) paradigm has been introduced as a promising interconnection solution to these systems.…”

Section: Introductionmentioning

confidence: 99%

Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

Belkacemi

Daoui

Bouzefrane

et al. 2019

International Journal of Distributed Systems and Technologies

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Mapping parallel applications onto a network on chip (NoC) that is based on heterogeneous MPSoCs is considered as an instance of an NP-hard and a multi-objective problem. Various multi-objective algorithms have been proposed in the literature to handle this issue. Metaheuristics stand out as highly appropriate approaches to deal with this kind of problem. These metaheuristics are classified into two sets: population-based metaheuristics and single solution-based ones. To take advantage of the both sets, the trend is to use hybrid solutions that have shown to give better results. In this article, the authors propose to hybridize these two metaheuristics sets to find good Pareto mapping solutions to optimize the execution time and the energy consumption simultaneously. The experimental results have shown that the proposed hybrid algorithms give high quality non-dominated mapping solutions in a reasonable runtime.

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Low Power Low Latency Floorplan‐aware Path Synthesis in Application-Specific Network-on-Chip Design

Cited by 7 publications

References 30 publications

A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on Chip

A Hybrid Selection Strategy Based on Traffic Analysis for Improving Performance in Networks on Chip

SB-Router: A Swapped Buffer Activated Low Latency Network-on-Chip Router

Parallel Applications Mapping onto Network on Chip Based on Heterogeneous MPSoCs Using Hybrid Algorithms

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