Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs

Zhuang, Haoyu; Tong, Can; Peng, Xizhu; Tang, He

doi:10.1109/tvlsi.2020.3021680

Cited by 16 publications

(7 citation statements)

References 17 publications

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“…An edge-race comparator (ERC), which is extremely suitable for low-power, high-resolution SAR ADCs, is proposed in this article [9]. It's not only low-power and low-noise but also doesn't need high-voltage headroom.…”

Section: An Edge-race Comparatormentioning

confidence: 99%

“…The supply voltage doesn't change too much, but the delay and energy consumption has greatly improved. [7] decrease the delay considerably at the cost of larger energy consumption while [9] guarantees the energy consumption but ignore the delay. Therefore, different performances of a device should be compromised to adapt to various work environments.…”

Section: 𝑡 (13)mentioning

confidence: 99%

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The Analysis of High-Speed Low-Power Dynamic Comparators

Chen¹,

Ni²,

Xiong³

2022

J. Phys.: Conf. Ser.

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This article reviews 5 different articles on optimizing comparators and focuses on their innovations. Many innovative methods are used to get a higher comparison speed, lower power consumption and degraded noise comparator. Many novel methods such as connecting the conventional two-stage dynamic comparator to a transconductance-enhanced latching stage, adding a charge pump to the Miyahara’s comparator, engendering two propagating edges in two inverter loops and measuring the distance between the two edges to compare different input voltage and using an inverter-based input pair which is powered by a floating reservoir capacitor can significantly achieve these goals. What’s more, a three-stage feedforward fully dynamic comparator with an extra parallel feedforward path, which is a completely innovatory and newly designed comparator, is also proposed.

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Section: An Edge-race Comparatormentioning

confidence: 99%

Section: 𝑡 (13)mentioning

confidence: 99%

The Analysis of High-Speed Low-Power Dynamic Comparators

Chen¹,

Ni²,

Xiong³

2022

J. Phys.: Conf. Ser.

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“…A hybrid comparator for high-resolution SAR ADC is discussed in [10,21]. A 14-bit SAR ADC employing two dynamic comparators is proposed.…”

Section: Literature Workmentioning

confidence: 99%

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Thamaraimanalan¹,

Venkatesan

2022

Preprint

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Comparator design is a major challenge during the implementation of high resolution SAR ADCs. In this research, a mutated dynamic power gated comparator is designed to achieve the SAR ADC with ultra-low power and enhanced gain. The proposed power gated comparator is designed using 45nm CMOS technology, and it is tested at 3.3V and 5V. High speed and low power are achieved through transistor sizing and power gating techniques. Mismatch of transistors, the offset value is appropriately calculated using the input resistance of the differential amplifier and trans conductance. Also, the offset cancellation and digital calibration techniques are included in the design to enhance the precision, and to improve the performance of ADCs. For the proposed comparator, phase margin, gain, ICMR, power consumption, offset voltage, slew rate, load capacitance, propagation delay, kickback noise, and settling time are compared with the conventional comparator. The proposed design consumes only 4.2mW while operating at 5V and 1.5mW when the input voltage is 3.3V. The effective resolution of the SAR ADC is observed as 8.2 bit with the proposed power gated comparator.

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“…By adjusting the comparison energy automatically with different input voltage, it greatly saved energy and optimizes the tunability with the input-referred noise. In 2020, H. Zhuang proposed the edge-race comparator (ERC) [7]. It compared the differential input voltage by generating two propagating edges in two inverter loops and measured the distance between them to determine the comparison result.…”

mentioning

confidence: 99%

“…Section 4 provides a brand-new perspective with the edge-pursuit comparator proposed by M. Shim [6]. In Section 5, the performance of H. Zhuang's edge-race comparator will be analysed quantificationally [7]. Comparisons for all the four innovative designs are mentioned in Table I in Section 6.…”

mentioning

confidence: 99%

Innovative Techniques in Comparator Designs

Chen

2022

J. Phys.: Conf. Ser.

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This paper presents four innovative designs of comparators proposed these years. A latch-type dynamic bias adds a tail capacitor to prevent fully discharging at the pre-amplifier output nodes to reduce energy consumption. The comparator is analysed and then compared with floating inverter amplifier (FIA) type. The pre-amplifier of the FIA type adopts an inverter-based input pair by a floating reservoir capacitor, greatly boosting gm/Id and improving the energy efficiency. The edge-pursuit comparator (EPC) provides a new perspective when designing comparators. According to the input difference, it will automatically adjust the comparison energy, avoiding wasting unnecessary energy spent on coarse comparison. Finally, for the edge-race comparator (ERC), it further improves the performance of saving energy and addressing the relatively long comparison time in the EPC.

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Low-Power, Low-Noise Edge-Race Comparator for SAR ADCs

Cited by 16 publications

References 17 publications

The Analysis of High-Speed Low-Power Dynamic Comparators

The Analysis of High-Speed Low-Power Dynamic Comparators

High resolution mutated dynamic precision power gated comparator for 9-bit SAR ADC

Innovative Techniques in Comparator Designs

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