Low-power, low-storage-overhead chipkill correct via multi-line error correction

Jian, Xun; Duwe, Henry; Sartori, John; Sridharan, Vilas; Kumar, Rakesh

doi:10.1145/2503210.2503243

Cited by 47 publications

(30 citation statements)

References 16 publications

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“…In addition to these commercial chipkill-correct schemes, there are a number of academic approaches (including Virtualized ECC [37], LOT-ECC [38] and Multi-ECC [39]) that use additional storage to provide strong, low-redundancy error protection.…”

Section: Multi-tiered Ecc Approachesmentioning

confidence: 99%

“…Such an approach (relying on a retirement scheme for permanent errors) seems consistent with the direction that industry has been moving, as is evidenced by Intel's DDDC/DDDC+1 scheme. It has also been employed by other recent academic ECC papers that have expensive correction procedures [39]. The flexible nature of Bamboo ECC codes is well suited to RBS-based retirement, as is demonstrated in Section 5.2.…”

Section: Overheadsmentioning

confidence: 99%

See 1 more Smart Citation

Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory

Kim

Sullivan

Erez

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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Section: Multi-tiered Ecc Approachesmentioning

confidence: 99%

Section: Overheadsmentioning

confidence: 99%

Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory

Kim

Sullivan

Erez

2015

2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA)

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“…For x4 DRAM systems, such a scheme is based on a 4-bit symbol code with 32 symbols for data and 4 symbols for ECC parity and provides single symbol correction and double symbol detection. It has to activate two ranks with 18 chips per rank per memory access resulting in high power consumption and poor timing performance [20,21]. In contrast, the proposed ECC schemes for regular and checkpoint data only activate a single x4 DRAM rank and have strong reliability due to the use of symbol-based codes that have been tailored for this application.…”

Section: Ecc Designmentioning

confidence: 99%

Checkpointing Exascale Memory Systems with Existing Memory Technologies

Abeyratne

Chen

et al. 2016

Proceedings of the Second International Symposium on Memory Systems

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Building exascale supercomputers requires resilience to failing components such as processor, memory, storage, and network devices. Checkpoint/restart is a key ingredient in attaining resilience, but providing fast and reliable checkpointing is becoming more challenging as the amount of data to checkpoint and the number of components that can fail increase in exascale systems. To improve the speed of checkpointing, emerging non-volatile memory (phase change, magnetic, resistive RAM) have been proposed. However, using unproven memories to create checkpoints will only increase the design risk for exascale memory systems. In this paper, we show that exascale systems with hundreds of petabytes of memory can be constructed with commodity DRAM and SSD flash memory and that newer non-volatile memory are unnecessary, at least for the next generation.The challenge when using commodity parts is providing fast and reliable checkpointing to protect against system failures. A straightforward solution of checkpointing to local flash-based SSD devices will not work because they are endurance and performance limited. We present a checkpointing solution that employs a combination of DRAM and SSD devices. A Checkpoint Location Controller (CLC) is implemented to monitor the endurance of the SSD and the performance loss of the application and to decide dynamically whether to checkpoint to the DRAM or the SSD.The CLC improves both SSD endurance and application slowdown; but the checkpoints in DRAM are exposed to device failures. To design a reliable exascale memory, we protect the data with a low latency ECC that can correct all errors due to bit/pin/column/word faults and also detect errors due to chip failures, and we protect the checkpoint with a Chipkill-Correct level ECC that allows reliable checkpointing to the DRAM.Using our system, the SSD lifetime increases by 2×-from 3 years to 6.3 years. Furthermore, the CLC reduces the average checkpointing overhead by nearly 10× (47% from a 420% slowdown), compared to when the application always checkpointed to the SSD.

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“…In addition, future systems may be better off decoupling detection from correction (e.g., [20]) in order to meet reliability targets.…”

Section: Case Study: Using Mb-avf For Designmentioning

confidence: 99%

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

Wilkening

Sridharan

et al. 2014

2014 47th Annual IEEE/ACM International Symposium on Microarchitecture

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Abstract-Reliability is an important design constraint in modern microprocessors, and one of the fundamental reliability challenges is combating the effects of transient faults. This requires extensive analysis, including significant fault modeling to allow architects to make informed reliability tradeoffs. Recent data shows that multi-bit transient faults are becoming more common, increasing from 0.5% of SRAM faults in 180nm to 3.9% in 22nm, and are predicted to be even more prevalent in smaller technology nodes. Therefore, accurately modeling the effects of multi-bit transient faults is increasingly important to the microprocessor design process.Architecture vulnerability factor (AVF) analysis is a method to model the effects of single-bit transient faults. In this paper, we propose a method to calculate AVFs for spatial multi-bit transient faults (MB-AVFs) and provide insights that can help reduce the impact of these faults. First, we describe a novel multi-bit AVF analysis approach for detected, uncorrected errors (DUEs) and show how to measure DUE MB-AVFs in a performance simulator. We then extend our approach to measure SDC MB-AVFs. We find that MB-AVFs are not derivable from single-bit AVFs. We also find that larger fault modes have higher MB-AVFs. Finally, we present a case study on using MB-AVF analysis to optimize processor design, yielding SDC reductions of 86% in a GPU vector register file.

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Low-power, low-storage-overhead chipkill correct via multi-line error correction

Cited by 47 publications

References 16 publications

Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory

Bamboo ECC: Strong, safe, and flexible codes for reliable computer memory

Checkpointing Exascale Memory Systems with Existing Memory Technologies

Calculating Architectural Vulnerability Factors for Spatial Multi-Bit Transient Faults

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